Jason Zhu 65bd598f41 clk: rockchip: rk3568: set the ACLK_BUS to 150MHz in spl ... Since the mcu uses the ACLK_BUS clock and 150MHz is need as default clock rate. Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Change-Id: I60c4603fa0c0b45667c6583992ea461fed18fcf5		2020-11-24 17:13:18 +08:00
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aspeed	…
at91	…
exynos	…
renesas	UPSTREAM: wait_bit: use wait_for_bit_le32 and remove wait_for_bit	2019-07-05 19:21:04 +08:00
rockchip	clk: rockchip: rk3568: set the ACLK_BUS to 150MHz in spl	2020-11-24 17:13:18 +08:00
tegra	…
uniphier	…
Kconfig	…
Makefile	…
clk-uclass.c	UPSTREAM: clk: Add get/enable/disable/release for a bulk of clocks	2020-01-07 17:24:50 +08:00
clk_bcm6345.c	…
clk_boston.c	…
clk_fixed_rate.c	…
clk_pic32.c	UPSTREAM: wait_bit: use wait_for_bit_le32 and remove wait_for_bit	2019-07-05 19:21:04 +08:00
clk_sandbox.c	…
clk_sandbox_test.c	UPSTREAM: clk: add clk_valid()	2020-06-02 16:07:42 +08:00
clk_stm32f7.c	…
clk_zynq.c	…
clk_zynqmp.c	…