335 lines
10 KiB
C
335 lines
10 KiB
C
/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/compiler.h>
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#include <efi_loader.h>
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#include <iomem.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_IRQ)
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int interrupt_init(void)
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{
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return 0;
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}
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void enable_interrupts(void)
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{
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return;
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}
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int disable_interrupts(void)
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{
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return 0;
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}
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#endif
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#if (!defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD))
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#define REG_BITS(val, shift, mask) (((val) >> (shift)) & (mask))
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void show_regs(struct pt_regs *regs)
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{
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int i;
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int el = current_el();
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const char *h_scr_name[] = {
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[2] = "HCR_EL2",
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[3] = "SCR_EL3",
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};
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const char *esr_bits_ec[] = {
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[0] = "EC[31:26] == 000000, Exception with an unknown reason",
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[1] = "EC[31:26] == 000001, Exception from a WFI or WFE instruction",
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[3] = "EC[31:26] == 000011, Exception from an MCR or MRC access",
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[4] = "EC[31:26] == 000100, Exception from an MCRR or MRRC access",
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[5] = "EC[31:26] == 000101, Exception from an MCR or MRC access",
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[6] = "EC[31:26] == 000110, Exception from an LDC or STC access to CP14",
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[7] = "EC[31:26] == 000111, Exception from an access to an Advanced SIMD or floating-point register, resulting from CPACR_EL1.FPEN or CPTR_ELx.TFP",
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[8] = "EC[31:26] == 001000, Exception from an MCR or MRC access",
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[12] = "EC[31:26] == 001100, Exception from an MCRR or MRRC access",
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[14] = "EC[31:26] == 001110, Exception from an Illegal execution state, or a PC or SP alignment fault",
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[10] = "EC[31:26] == 010001, Exception from HVC or SVC instruction execution",
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[18] = "EC[31:26] == 010010, Exception from HVC or SVC instruction execution",
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[19] = "EC[31:26] == 010011, Exception from SMC instruction execution in AArch32 state",
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[21] = "EC[31:26] == 010101, Exception from HVC or SVC instruction execution",
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[22] = "EC[31:26] == 010110, Exception from HVC or SVC instruction execution",
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[23] = "EC[31:26] == 010111, Exception from SMC instruction execution in AArch64 state",
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[24] = "EC[31:26] == 011000, Exception from MSR, MRS, or System instruction execution in AArch64 state",
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[31] = "EC[31:26] == 011111, IMPLEMENTATION DEFINED exception to EL3",
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[32] = "EC[31:26] == 100000, Exception from an Instruction abort",
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[33] = "EC[31:26] == 100001, Exception from an Instruction abort",
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[34] = "EC[31:26] == 100010, Exception from an Illegal execution state, or a PC or SP alignment fault",
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[36] = "EC[31:26] == 100100, Exception from a Data abort, from lower exception level",
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[37] = "EC[31:26] == 100101, Exception from a Data abort, from current exception level",
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[38] = "EC[31:26] == 100110, Exception from an Illegal execution state, or a PC or SP alignment fault",
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[40] = "EC[31:26] == 101000, Exception from a trapped Floating-point exception",
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[44] = "EC[31:26] == 101100, Exception from a trapped Floating-point exception",
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[47] = "EC[31:26] == 101111, SError interrupt",
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[48] = "EC[31:26] == 110000, Exception from a Breakpoint or Vector Catch debug event",
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[49] = "EC[31:26] == 110001, Exception from a Breakpoint or Vector Catch debug event",
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[50] = "EC[31:26] == 110010, Exception from a Software Step debug event",
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[51] = "EC[31:26] == 110011, Exception from a Software Step debug event",
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[52] = "EC[31:26] == 110100, Exception from a Watchpoint debug event",
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[53] = "EC[31:26] == 110101, Exception from a Watchpoint debug event",
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[56] = "EC[31:26] == 111000, Exception from execution of a Software Breakpoint instructio",
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};
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const char *esr_bits_il[] = {
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"IL[25] == 0, 16-bit instruction trapped",
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"IL[25] == 1, 32-bit instruction trapped",
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};
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const char *daif_bits_f[] = {
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"F[6] == 0, FIQ not masked",
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"F[6] == 1, FIQ masked",
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};
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const char *daif_bits_i[] = {
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"I[7] == 0, IRQ not masked",
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"I[7] == 1, IRQ masked",
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};
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const char *daif_bits_a[] = {
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"A[8] == 0, ABORT not masked",
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"A[8] == 1, ABORT masked",
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};
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const char *daif_bits_d[] = {
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"D[9] == 0, DBG not masked",
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"D[9] == 1, DBG masked",
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};
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const char *spsr_bits_m_aarch32[] = {
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[0] = "M[3:0] == 0000, User",
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[1] = "M[3:0] == 0001, FIQ",
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[2] = "M[3:0] == 0010, IRQ",
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[3] = "M[3:0] == 0011, Supervisor",
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[6] = "M[3:0] == 0110, Monitor",
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[7] = "M[3:0] == 0111, Abort",
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[10] = "M[3:0] == 1010, Hyp",
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[11] = "M[3:0] == 1011, Undefined",
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[15] = "M[3:0] == 1111, System",
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};
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const char *spsr_bits_m_aarch64[] = {
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[0] = "M[3:0] == 0000, EL0t",
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[4] = "M[3:0] == 0100, EL1t",
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[5] = "M[3:0] == 0101, EL1h",
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[8] = "M[3:0] == 1000, EL2t",
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[9] = "M[3:0] == 1001, EL2h",
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[10] = "M[3:0] == 1100, EL3t",
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[11] = "M[3:0] == 1101, EL3h",
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};
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const char *spsr_bits_m[] = {
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"M[4] == 0, Exception taken from AArch64",
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"M[4] == 1, Exception taken from AArch32",
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};
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const char *spsr_bits_f[] = {
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"F[6] == 0, FIQ not masked",
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"F[6] == 1, FIQ masked",
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};
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const char *spsr_bits_i[] = {
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"I[7] == 0, IRQ not masked",
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"I[7] == 1, IRQ masked",
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};
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const char *spsr_bits_a[] = {
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"A[8] == 0, ABORT not masked",
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"A[8] == 1, ABORT masked",
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};
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const char *spsr_bits_d[] = {
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"D[9] == 0, DBG not masked",
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"D[9] == 1, DBG masked",
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};
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const char *sctlr_bits_i[] = {
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"I[12] == 0, Icache disabled",
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"I[12] == 1, Icaches enabled",
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};
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const char *sctlr_bits_c[] = {
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"C[2] == 0, Dcache disabled",
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"C[2] == 1, Dcache enabled",
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};
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const char *sctlr_bits_m[] = {
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"M[0] == 0, MMU disabled",
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"M[0] == 1, MMU enabled",
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};
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printf("* Relocate offset = %016lx\n", gd->reloc_off);
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if (gd->flags & GD_FLG_RELOC) {
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printf("* ELR(PC) = %016lx\n", regs->elr - gd->reloc_off);
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printf("* LR = %016lx\n", regs->regs[30] - gd->reloc_off);
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} else {
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printf("* ELR(PC) = %016lx\n", regs->elr);
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printf("* LR = %016lx\n", regs->regs[30]);
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}
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printf("* SP = %016lx\n", regs->sp);
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printf("\n");
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/*
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* System registers
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*/
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/* ESR_EL2 */
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printf("* ESR_EL%d = %016lx\n", el, regs->esr);
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printf("\t%s\n", esr_bits_ec[REG_BITS(regs->esr, 26, 0x3f)]);
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printf("\t%s\n", esr_bits_il[REG_BITS(regs->esr, 25, 0x01)]);
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printf("\n");
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/* DAIF */
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printf("* DAIF = %016lx\n", regs->daif);
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printf("\t%s\n", daif_bits_d[REG_BITS(regs->daif, 9, 0x1)]);
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printf("\t%s\n", daif_bits_a[REG_BITS(regs->daif, 8, 0x1)]);
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printf("\t%s\n", daif_bits_i[REG_BITS(regs->daif, 7, 0x1)]);
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printf("\t%s\n", daif_bits_f[REG_BITS(regs->daif, 6, 0x1)]);
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printf("\n");
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/* SPSR_ELx */
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printf("* SPSR_EL%d = %016lx\n", el, regs->spsr);
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printf("\t%s\n", spsr_bits_d[REG_BITS(regs->spsr, 9, 0x1)]);
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printf("\t%s\n", spsr_bits_a[REG_BITS(regs->spsr, 8, 0x1)]);
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printf("\t%s\n", spsr_bits_i[REG_BITS(regs->spsr, 7, 0x1)]);
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printf("\t%s\n", spsr_bits_f[REG_BITS(regs->spsr, 6, 0x1)]);
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printf("\t%s\n", spsr_bits_m[REG_BITS(regs->spsr, 4, 0x1)]);
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if (REG_BITS(regs->spsr, 4, 0x1))
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printf("\t%s\n", spsr_bits_m_aarch32[REG_BITS(regs->spsr, 0, 0xf)]);
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else
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printf("\t%s\n", spsr_bits_m_aarch64[REG_BITS(regs->spsr, 0, 0xf)]);
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printf("\n");
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/* SCTLR_EL2 */
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printf("* SCTLR_EL%d = %016lx\n", el, regs->sctlr);
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printf("\t%s\n", sctlr_bits_i[REG_BITS(regs->sctlr, 12, 0x1)]);
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printf("\t%s\n", sctlr_bits_c[REG_BITS(regs->sctlr, 2, 0x1)]);
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printf("\t%s\n", sctlr_bits_m[REG_BITS(regs->sctlr, 0, 0x1)]);
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printf("\n");
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/* Other */
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if (el >= 2)
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printf("* %s = %016lx\n", h_scr_name[el], regs->hcr);
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printf("* VBAR_EL%d = %016lx\n", el, regs->vbar);
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printf("* TTBR0_EL%d = %016lx\n", el, regs->ttbr0);
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printf("\n");
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for (i = 0; i < 29; i += 2)
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printf("x%-2d: %016lx x%-2d: %016lx\n",
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i, regs->regs[i], i+1, regs->regs[i+1]);
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printf("\n");
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iomem_show("SP", regs->sp, 0x00, 0xfc);
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printf("\n");
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#ifdef CONFIG_ROCKCHIP_CRASH_DUMP
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iomem_show_by_compatible("-cru", 0, 0x400);
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iomem_show_by_compatible("-pmucru", 0, 0x400);
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iomem_show_by_compatible("-grf", 0, 0x400);
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iomem_show_by_compatible("-pmugrf", 0, 0x400);
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/* tobe add here ... */
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#endif
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}
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#else
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void show_regs(struct pt_regs *regs)
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{
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int i;
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if (gd->flags & GD_FLG_RELOC) {
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printf("ELR: %lx\n", regs->elr - gd->reloc_off);
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printf("LR: %lx\n", regs->regs[30] - gd->reloc_off);
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} else {
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printf("ELR: %lx\n", regs->elr);
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printf("LR: %lx\n", regs->regs[30]);
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}
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for (i = 0; i < 29; i += 2)
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printf("x%-2d: %016lx x%-2d: %016lx\n",
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i, regs->regs[i], i+1, regs->regs[i+1]);
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printf("\n");
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}
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#endif
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/*
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* do_bad_sync handles the impossible case in the Synchronous Abort vector.
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*/
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void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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/*
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* do_bad_irq handles the impossible case in the Irq vector.
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*/
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void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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/*
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* do_bad_fiq handles the impossible case in the Fiq vector.
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*/
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void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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/*
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* do_bad_error handles the impossible case in the Error vector.
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*/
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void do_bad_error(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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/*
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* do_sync handles the Synchronous Abort exception.
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*/
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void do_sync(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_IRQ)
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/*
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* do_irq handles the Irq exception.
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*/
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void do_irq(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("\"Irq\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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#endif
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/*
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* do_fiq handles the Fiq exception.
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*/
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void do_fiq(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("\"Fiq\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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/*
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* do_error handles the Error exception.
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* Errors are more likely to be processor specific,
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* it is defined with weak attribute and can be redefined
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* in processor specific code.
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*/
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void __weak do_error(struct pt_regs *pt_regs, unsigned int esr)
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{
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efi_restore_gd();
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printf("\"Error\" handler, esr 0x%08x\n", esr);
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show_regs(pt_regs);
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panic("Resetting CPU ...\n");
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}
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