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Stefan Roese a2c95a7224 PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance 
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
 		2006-07-28 18:34:58 +02:00
..
bamboo AMCC bamboo (440EP) U-Boot image reduced to 384kbyte 2006-07-27 16:14:05 +02:00
bubinga 2005-12-12 16:06:05 +01:00
common Add support for AMCC Bamboo PPC440EP eval board 2005-08-04 17:09:16 +02:00
ebony GCC-4.x fixes: clean up global data pointer initialization for all boards. 2006-03-31 18:32:53 +02:00
luan GCC-4.x fixes: clean up global data pointer initialization for all boards. 2006-03-31 18:32:53 +02:00
ocotea GCC-4.x fixes: clean up global data pointer initialization for all boards. 2006-03-31 18:32:53 +02:00
walnut GCC-4.x fixes: clean up global data pointer initialization for all boards. 2006-03-31 18:32:53 +02:00
yellowstone PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance 2006-07-28 18:34:58 +02:00
yosemite PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance 2006-07-28 18:34:58 +02:00
yucca Add support for TB5200 board 2006-07-19 13:50:38 +02:00