66869f9554
Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun <yorksun@freescale.com> |
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| .. | ||
| Makefile | ||
| arm_ddr_gen3.c | ||
| ctrl_regs.c | ||
| ddr1_dimm_params.c | ||
| ddr2_dimm_params.c | ||
| ddr3_dimm_params.c | ||
| ddr4_dimm_params.c | ||
| fsl_ddr_gen4.c | ||
| interactive.c | ||
| lc_common_dimm_params.c | ||
| main.c | ||
| mpc85xx_ddr_gen1.c | ||
| mpc85xx_ddr_gen2.c | ||
| mpc85xx_ddr_gen3.c | ||
| mpc86xx_ddr.c | ||
| options.c | ||
| util.c | ||