Yu YongZhen f992fe3334 clk: rockchip: rk3308: Make DCLK_VOP clock id consistent with kernel ... Change-Id: I3e5b042a5e7b4bd4a7724451b30cfa9601955541 Signed-off-by: Yu YongZhen <yuyz@rock-chips.com>		2019-04-16 09:06:52 +08:00
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clk	…
clock	clk: rockchip: rk3308: Make DCLK_VOP clock id consistent with kernel	2019-04-16 09:06:52 +08:00
comphy	phy: marvell: cp110: add 5G XFI mode	2017-05-09 13:38:18 +02:00
dma	…
gpio	…
input	…
interrupt-controller	…
interrupt-router	…
mailbox	…
media	rockchip: include: add some define for mipi dsi	2017-11-29 16:19:00 +08:00
memory	rockchip: rk3368: add DRAM controller driver with DRAM initialisation	2017-08-13 17:12:33 +02:00
mfd	ARM: DTS: stm32: align DT clock declaration with kernel	2017-07-26 11:26:52 -04:00
mrc	…
net	…
phy	…
pinctrl	rockchip: dts: rk3399: sync with kernel dts	2017-05-10 13:37:21 -06:00
pmic	…
power	rockchip: dtsi: rk1808: sync from kernel	2018-09-29 10:33:04 +08:00
power-domain	mips: bmips: add bcm6328-power-domain driver support for BCM63268	2017-05-10 16:16:09 +02:00
pwm	…
regulator	…
reset	ARM64: dts: hi3798cv200-poplar: add device tree bindings	2017-07-10 14:26:02 -04:00
soc	rockchip: dts: px30: add px30-evb dts	2018-02-05 20:55:54 +08:00
sound	…
thermal	…
video	…