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Shengzhou Liu 1a87c24fe8 armv8: fsl-layerscape: Update ddr erratum a008336 
DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
 		2016-09-14 14:05:20 -07:00
..
arc arc: Rename AXS101 board to more generic AXS10x 2016-08-05 12:50:33 +03:00
arm armv8: fsl-layerscape: Update ddr erratum a008336 2016-09-14 14:05:20 -07:00
avr32
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blackfin
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m68k net: mii: Changes not made by spatch 2016-08-15 15:29:03 -05:00
microblaze
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mips net: mii: Use spatch to update miiphy_register 2016-08-15 15:26:33 -05:00
nds32
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nios2
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openrisc
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powerpc net: mii: Changes not made by spatch 2016-08-15 15:29:03 -05:00
sandbox cmd: Split 'bootz' and 'booti' out from 'bootm' 2016-08-20 11:35:07 -04:00
sh
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sparc
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x86 x86: efi: Fix EFI 64-bit payload build warnings 2016-08-30 09:26:05 +08:00
xtensa xtensa: add support for the 'xtfpga' evaluation board 2016-08-15 18:46:40 -04:00
.gitignore
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Kconfig xtensa: add support for the xtensa processor architecture [2/2] 2016-08-15 18:46:38 -04:00