Elaine Zhang 62be0c2c53 clk: rockchip: rk3368: support get pll config by table ... add some special pll configs for better clock jitter. Change-Id: I3484d36feb9f4b99a42a2ba532ae2015968d83ff Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>		2020-09-04 14:22:54 +08:00
..
aspeed	…
at91	…
exynos	…
renesas	UPSTREAM: wait_bit: use wait_for_bit_le32 and remove wait_for_bit	2019-07-05 19:21:04 +08:00
rockchip	clk: rockchip: rk3368: support get pll config by table	2020-09-04 14:22:54 +08:00
tegra	…
uniphier	…
Kconfig	…
Makefile	…
clk-uclass.c	UPSTREAM: clk: Add get/enable/disable/release for a bulk of clocks	2020-01-07 17:24:50 +08:00
clk_bcm6345.c	…
clk_boston.c	…
clk_fixed_rate.c	clk: Remove superfluous gd declarations	2018-02-24 19:02:43 +08:00
clk_pic32.c	UPSTREAM: wait_bit: use wait_for_bit_le32 and remove wait_for_bit	2019-07-05 19:21:04 +08:00
clk_sandbox.c	…
clk_sandbox_test.c	UPSTREAM: clk: add clk_valid()	2020-06-02 16:07:42 +08:00
clk_stm32f7.c	…
clk_zynq.c	…
clk_zynqmp.c	…