474 lines
11 KiB
C
474 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1808_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK1808_H
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_GPLL 4
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#define PLL_NPLL 5
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#define PLL_PPLL 6
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#define ARMCLK 7
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#define DCLK_VOPRAW 10
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#define DCLK_VOPLITE 11
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#define DCLK_CIF 12
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#define XIN24M_DIV 13
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/* sclk (special clocks) */
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#define USB480M 20
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#define SCLK_PVTM_CORE 21
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#define SCLK_NPU 22
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#define SCLK_PVTM_NPU 23
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#define SCLK_DDRCLK 24
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#define SCLK_I2S0_8CH_TX_MUX 25
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#define SCLK_I2S0_8CH_RX_MUX 26
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#define SCLK_RTC32K_PMU 27
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#define SCLK_TXESC 28
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#define SCLK_RGA 29
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#define SCLK_ISP 30
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#define SCLK_CIF_OUT 31
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#define SCLK_PCIE_AUX 32
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#define SCLK_USB3_OTG0_REF 33
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#define SCLK_USB3_OTG0_SUSPEND 34
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#define SCLK_SDIO_DIV 35
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#define SCLK_SDIO_DIV50 36
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#define SCLK_SDIO 37
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#define SCLK_SDIO_DRV 38
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#define SCLK_SDIO_SAMPLE 39
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#define SCLK_EMMC_DIV 40
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#define SCLK_EMMC_DIV50 41
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#define SCLK_EMMC 42
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#define SCLK_EMMC_DRV 43
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#define SCLK_EMMC_SAMPLE 44
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#define SCLK_SDMMC_DIV 45
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#define SCLK_SDMMC_DIV50 46
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#define SCLK_SDMMC 47
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#define SCLK_SDMMC_DRV 48
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#define SCLK_SDMMC_SAMPLE 49
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#define SCLK_SFC 50
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#define SCLK_GMAC_OUT 51
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#define SCLK_GMAC_SRC 52
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#define SCLK_GMAC 53
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#define SCLK_GMAC_REF 54
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#define SCLK_GMAC_REFOUT 55
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#define SCLK_GMAC_RGMII_SPEED 56
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#define SCLK_GMAC_RMII_SPEED 57
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#define SCLK_GMAC_RX_TX 58
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#define SCLK_CRYPTO 59
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#define SCLK_CRYPTO_APK 60
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#define SCLK_UART1 61
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#define SCLK_UART2 62
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#define SCLK_UART3 63
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#define SCLK_UART4 64
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#define SCLK_UART5 65
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#define SCLK_UART6 66
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#define SCLK_UART7 67
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#define SCLK_I2C1 68
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#define SCLK_I2C2 69
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#define SCLK_I2C3 70
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#define SCLK_I2C4 71
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#define SCLK_I2C5 72
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#define SCLK_SPI0 73
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#define SCLK_SPI1 74
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#define SCLK_SPI2 75
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#define SCLK_TSADC 76
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#define SCLK_SARADC 77
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#define SCLK_EFUSE_S 78
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#define SCLK_EFUSE_NS 79
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#define DBCLK_GPIO1 80
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#define DBCLK_GPIO2 81
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#define DBCLK_GPIO3 82
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#define DBCLK_GPIO4 83
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#define SCLK_PWM0 84
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#define SCLK_PWM1 85
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#define SCLK_PWM2 86
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#define SCLK_TIMER0 87
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#define SCLK_TIMER1 88
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#define SCLK_TIMER2 89
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#define SCLK_TIMER3 90
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#define SCLK_TIMER4 91
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#define SCLK_TIMER5 92
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#define SCLK_PDM 93
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#define SCLK_I2S0_8CH_TX_SRC 94
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#define SCLK_I2S0_8CH_TX 95
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#define SCLK_I2S0_8CH_TX_OUT 96
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#define SCLK_I2S0_8CH_RX_SRC 97
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#define SCLK_I2S0_8CH_RX 98
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#define SCLK_I2S0_8CH_RX_OUT 99
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#define SCLK_I2S1_2CH_SRC 100
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#define SCLK_I2S1_2CH 101
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#define SCLK_I2S1_2CH_OUT 102
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#define SCLK_WIFI_PMU 103
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#define SCLK_UART0_PMU 104
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#define SCLK_PVTM_PMU 105
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#define SCLK_PMU_I2C0 106
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#define DBCLK_PMU_GPIO0 107
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#define SCLK_REF24M_PMU 108
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#define SCLK_USBPHY_REF 109
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#define SCLK_MIPIDSIPHY_REF 110
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#define SCLK_PCIEPHY_REF 111
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#define SCLK_RTC32K_FRAC 112
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#define SCLK_32K_IOE 113
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/* aclk gates */
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#define ACLK_GIC_PRE 145
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#define ACLK_GIC 146
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#define ACLK_VPU 147
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#define ACLK_NPU 148
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#define ACLK_IMEM_PRE 153
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#define ACLK_IMEM0 154
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#define ACLK_IMEM1 155
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#define ACLK_IMEM2 156
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#define ACLK_IMEM3 157
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#define HSCLK_VIO 158
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#define ACLK_VOPRAW 159
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#define ACLK_VOPLITE 160
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#define ACLK_RGA 161
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#define ACLK_ISP 162
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#define ACLK_CIF 163
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#define HSCLK_PCIE 164
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#define ACLK_USB3OTG 165
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#define ACLK_PCIE 166
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#define ACLK_PCIE_MST 167
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#define ACLK_PCIE_SLV 168
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#define MSCLK_PERI 169
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#define ACLK_GMAC 170
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#define HSCLK_BUS_PRE 171
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#define ACLK_CRYPTO 172
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#define ACLK_DCF 173
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#define ACLK_DMAC 174
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/* hclk gates */
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#define HCLK_NPU 199
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#define HCLK_VPU 200
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#define LSCLK_VIO 201
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#define HCLK_VOPRAW 202
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#define HCLK_VOPLITE 203
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#define HCLK_RGA 204
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#define HCLK_ISP 205
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#define LSCLK_PCIE 206
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#define HCLK_HOST 207
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#define LSCLK_PERI 208
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#define HCLK_SDIO 209
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#define HCLK_EMMC 210
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#define HCLK_SDMMC 211
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#define HCLK_SFC 212
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#define MSCLK_BUS_PRE 213
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#define HCLK_ROM 214
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#define HCLK_CRYPTO 215
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#define HCLK_VAD 216
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#define HCLK_PDM 217
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#define HCLK_I2S0_8CH 218
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#define HCLK_I2S1_2CH 219
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#define MSCLK_CORE_NIU 220
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#define HSCLK_IMEM 221
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#define HCLK_HOST_ARB 222
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#define HCLK_CIF 223
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/* pclk gates */
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#define PCLK_DDR 250
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#define PCLK_DSI_TX 251
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#define PCLK_CSI_TX 252
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#define PCLK_CSI2HOST 253
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#define PCLK_PCIE 254
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#define PCLK_GMAC 255
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#define LSCLK_BUS_PRE 256
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#define PCLK_DCF 257
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#define PCLK_UART1 258
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#define PCLK_UART2 259
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#define PCLK_UART3 260
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#define PCLK_UART4 261
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#define PCLK_UART5 262
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#define PCLK_UART6 263
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#define PCLK_UART7 264
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#define PCLK_I2C1 265
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#define PCLK_I2C2 266
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#define PCLK_I2C3 267
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#define PCLK_I2C4 268
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#define PCLK_I2C5 269
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#define PCLK_SPI0 270
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#define PCLK_SPI1 271
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#define PCLK_SPI2 272
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#define PCLK_TSADC 273
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#define PCLK_SARADC 274
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#define PCLK_EFUSE 275
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#define PCLK_GPIO1 276
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#define PCLK_GPIO2 277
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#define PCLK_GPIO3 278
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#define PCLK_GPIO4 279
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#define PCLK_PWM0 280
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#define PCLK_PWM1 281
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#define PCLK_PWM2 282
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#define PCLK_TIMER 283
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#define PCLK_WDT 284
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#define PCLK_MIPIDSIPHY 285
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#define PCLK_MIPICSIPHY 286
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#define PCLK_DDRMON 287
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#define PCLK_DDRC 289
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#define PCLK_MSCH 290
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#define PCLK_STDBY 291
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#define PCLK_GPIO0_PMU 292
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#define PCLK_UART0_PMU 293
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#define PCLK_I2C0_PMU 294
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#define PCLK_USB3PHY_PIPE 295
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#define PCLK_PMU_PRE 296
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#define CLK_NR_CLKS (PCLK_PMU_PRE + 1)
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/* soft-reset indices */
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/* cru_softrst_con0 */
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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#define SRST_CORE0 2
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#define SRST_CORE1 3
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#define SRST_CORE0_DBG 4
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#define SRST_CORE1_DBG 5
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#define SRST_TOPDBG 6
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#define SRST_CORE_NOC 7
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#define SRST_STRC_A 8
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#define SRST_L2C 9
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#define SRST_DAP 10
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#define SRST_CORE_MSNIU 11
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#define SRST_GIC2CORE 12
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#define SRST_CORE2GIC 13
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#define SRST_CORE_PRF_A 14
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#define SRST_CORE_GRF_P 15
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/* cru_softrst_con1 */
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#define SRST_DDRPHY 16
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#define SRST_DDRPHY_P 18
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#define SRST_UPCTL2 20
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#define SRST_UPCTL2_A 21
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#define SRST_UPCTL2_P 22
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#define SRST_MSCH 23
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#define SRST_MSCH_P 24
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#define SRST_DDRMON_P 25
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#define SRST_DDRSTDBY_P 26
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#define SRST_DDRSTDBY 27
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#define SRST_DDRGRF_P 28
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#define SRST_AXI_SPLIT_A 29
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#define SRST_DDRDFI_CTL 30
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#define SRST_DDRDFI_CTL_P 31
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/* cru_softrst_con2 */
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#define SRST_GIC500_NIU_A 32
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#define SRST_GIC500_A 33
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#define SRST_GIC_CORE2GIC 34
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#define SRST_GIC_GIC2CORE 35
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#define SRST_NPU_CORE 36
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#define SRST_NPU_A 37
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#define SRST_NPU_H 38
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#define SRST_NPU_NIU_A 39
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#define SRST_NPU_NIU_H 40
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#define SRST_NPU2MEM_A 41
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#define SRST_NPU_PVTM 42
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#define SRST_CORE_PVTM 43
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#define SRST_GIC_SPINLOCK_A 47
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/* cru_softrst_con3 */
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#define SRST_PCIE_NIU_H 48
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#define SRST_PCIE_NIU_L 49
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#define SRST_PCIEGRF_P 50
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#define SRST_PCIECTL_P 51
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#define SRST_PCIECTL_POWERUP 52
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#define SRST_PCIECTL_MST_A 53
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#define SRST_PCIECTL_SLV_A 54
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#define SRST_PCIECTL_DBI_A 55
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#define SRST_PCIECTL_BUTTON 56
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#define SRST_PCIECTL_PE 57
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#define SRST_PCIECTL_CORE 58
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#define SRST_PCIECTL_NSTICKY 59
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#define SRST_PCIECTL_STICKY 60
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#define SRST_PCIECTL_PWR 61
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#define SRST_PCIE_NIU_A 62
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#define SRST_PCIE_NIU_P 63
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/* cru_softrst_con4 */
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#define SRST_PCIEPHY_POR 64
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#define SRST_PCIEPHY_P 65
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#define SRST_PCIEPHY_PIPE 66
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#define SRST_USBPHY_POR 67
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#define SRST_USBPHY_OTG_PORT 68
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#define SRST_USBPHY_HOST_PORT 69
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#define SRST_USB3PHY_GRF_P 70
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#define SRST_USB2PHY_GRF_P 71
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#define SRST_USB3_OTG_A 72
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#define SRST_USB2HOST_H 73
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#define SRST_USB2HOST_ARB_H 74
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#define SRSTUSB2HOST_UTMI 75
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/* cru_softrst_con5 */
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#define SRST_IMEM0_A 80
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#define SRST_IMEM1_A 81
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#define SRST_IMEM2_A 82
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#define SRST_IMEM3_A 83
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#define SRST_IMEM0_NIU_A 84
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#define SRST_IMEM1_NIU_A 85
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#define SRST_IMEM2_NIU_A 86
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#define SRST_IMEM3_NIU_A 87
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#define SRST_IMEM_NIU_H 88
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#define SRST_VPU_NIU_A 92
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#define SRST_VPU_NIU_H 93
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#define SRST_VPU_A 94
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#define SRST_VPU_H 95
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/* cru_softrst_con6 */
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#define SRST_VIO_NIU_H 96
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#define SRST_VIO_NIU_L 97
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#define SRST_VOPRAW_A 98
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#define SRST_VOPRAW_H 99
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#define SRST_VOPRAW_D 100
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#define SRST_VOPLITE_A 101
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#define SRST_VOPLITE_H 102
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#define SRST_VOPLITE_D 103
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#define SRST_MIPIDSI_HOST_P 104
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#define SRST_CSITX_P 105
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#define SRST_CSITX_TXBYTEHS 106
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#define SRST_CSITX_TXESC 107
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#define SRST_CSITX_CAM 108
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#define SRST_CSITX_I 109
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/* cru_softrst_con7 */
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#define SRST_RGA_A 112
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#define SRST_RGA_H 113
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#define SRST_RGA 114
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#define SRST_CSI2HOST_P 115
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#define SRST_CIF_A 116
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#define SRST_CIF_H 117
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#define SRST_CIF_I 118
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#define SRST_CIF_PCLKIN 119
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#define SRST_CIF_D 120
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#define SRST_ISP_H 121
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#define SRST_ISP 122
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#define SRST_MIPICSIPHY_P 124
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#define SRST_MIPIDSIPHY_P 125
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/* cru_softrst_con8 */
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#define SRST_PERI_NIU_H 128
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#define SRST_PERI_NIU_L 129
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#define SRST_PDMMC_NIU_H 132
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#define SRST_SDMMC_H 133
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#define SRST_SDIO_H 134
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#define SRST_EMMC_H 135
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#define SRST_SFC_H 136
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#define SRST_SFC 137
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#define SRST_GMAC_NIU_A 140
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#define SRST_GMAC_NIU_H 141
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#define SRST_GMAC_NIU_P 142
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#define SRST_GAMC_A 143
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/* cru_softrst_con9 */
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#define SRST_PMU_NIU_P 144
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#define SRST_PMU_SGRF_P 145
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#define SRST_PMU_GRF_P 146
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#define SRST_PMU_PMU 147
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#define SRST_PMU_MEM_P 148
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#define SRST_PMU_GPIO0_P 149
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#define SRST_PMU_UART0_P 150
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#define SRST_PMU_CRU 151
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#define SRST_PMU_PVTM 152
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#define SRST_PMU_UART0 153
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#define SRST_PMU_NIU_H 154
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#define SRST_PMU_DDR_FAIL_SAVE 155
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#define SRST_PMU_I2C0_P 156
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#define SRST_PMU_I2C0 157
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#define SRST_PMU_GPIO0_DB 158
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/* cru_softrst_con10 */
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#define SRST_AUDIO_NIU_H 160
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#define SRST_VAD_H 161
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#define SRST_PDM_H 162
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#define SRST_PDM 163
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#define SRST_I2S0_H 164
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#define SRST_I2S0_TX 165
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#define SRST_I2S1_H 166
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#define SRST_I2S1 167
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#define SRST_I2S0_RX 168
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/* cru_softrst_con11 */
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#define SRST_BUS_NIU_M 176
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#define SRST_BUS_NIU_L 177
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#define SRST_TOP_NIU_P 178
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#define SRST_ROM_H 179
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#define SRST_CRYPTO_A 180
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#define SRST_CRYPTO_H 181
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#define SRST_CRYPTO_CORE 182
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#define SRST_CRYPTO_APK 183
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#define SRST_DCF_A 184
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#define SRST_DCF_P 185
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#define SRST_UART1_P 186
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#define SRST_UART1 187
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#define SRST_UART2_P 188
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#define SRST_UART2 189
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#define SRST_UART3_P 190
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#define SRST_UART3 191
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/* cru_softrst_con12 */
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#define SRST_UART4_P 192
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#define SRST_UART4 193
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#define SRST_UART5_P 194
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#define SRST_UART5 195
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#define SRST_UART6_P 196
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#define SRST_UART6 197
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#define SRST_UART7_P 198
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#define SRST_UART7 199
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#define SRST_I2C1_P 200
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#define SRST_I2C1 201
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#define SRST_I2C2_P 202
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#define SRST_I2C2 203
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#define SRST_I2C3_P 204
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#define SRST_I2C3 205
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#define SRST_PWM0_P 206
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#define SRST_PWM0 207
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/* cru_softrst_con13 */
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#define SRST_PWM1_P 208
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#define SRST_PWM1 209
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#define SRST_PWM2_P 210
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#define SRST_PWM2 211
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#define SRST_SPI0_P 212
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#define SRST_SPI0 213
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#define SRST_SPI1_P 214
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#define SRST_SPI1 215
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#define SRST_SPI2_P 216
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#define SRST_SPI2 217
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#define SRST_BUS_SGRF_P 218
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#define SRST_BUS_GRF_P 219
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#define SRST_TIMER_P 220
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#define SRST_TIMER0 221
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#define SRST_TIMER1 222
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#define SRST_TIMER2 223
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/* cru_softrst_con14 */
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#define SRST_TIMER3 224
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#define SRST_TIMER4 225
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#define SRST_TIMER5 226
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#define SRST_WDT_NS_P 227
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#define SRST_EFUSE_NS_P 228
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#define SRST_EFUSE_NS 229
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#define SRST_GPIO1_P 230
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#define SRST_GPIO1_DB 231
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#define SRST_GPIO2_P 232
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#define SRST_GPIO2_DB 233
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#define SRST_GPIO3_P 234
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#define SRST_GPIO3_DB 235
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#define SRST_GPIO4_P 236
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#define SRST_GPIO4_DB 237
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#define SRST_BUS_SUB_NIU_M 238
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/* cru_softrst_con15 */
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#define SRST_I2C4_P 240
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#define SRST_I2C4 241
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#define SRST_I2C5_P 242
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#define SRST_I2C5 243
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#define SRST_SARADC 252
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#define SRST_SARADC_P 253
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#define SRST_TSADC_P 254
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#define SRST_TSADC 255
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#endif
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