Add support for USB3 host and gadget driver. This is a direct sync of
Linux kernel Cadence USB stack that from v5.4-rc1 release.
Driver has been modified so that it compiles without errors against
U-Boot code base.
Features not required for U-Boot such as scatter-gather DMA and OTG
interrupt handling has been dropped.
Change-Id: I168e032f35d259ad1bb7a7f9f3c066bd13f129d4
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
[jjhiblot@ti.com: Add PHY support]
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 7e91f6ccdc84fe5952e5c26769e65d12e5fc4733)
This patch was copied from kernel commit: 67fdfda4a99ed.
Sometimes, the gadget driver we want to run has max_speed lower than
what the UDC supports. In such situations, UDC might want to make sure
we don't try to connect on speeds not supported by the gadget
driver because that will just fail.
So here introduce a new optional ->udc_set_speed() method which can be
implemented by interested UDC drivers to achieve this purpose.
Change-Id: I8ce57970c9095a92553ee12520e3724bd029d6b6
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 8d94e184ffdef48b40942c12d9e7b0290e60a1ef)
Add match_ep() op to usb_gadget_ops similar to Linux kernel which is
useful in finding a suitable ep match for the function driver. This will
avoid adding more gadget_is_xxx() handling code to usb_ep_autoconfig().
Also sync usb_ep_caps struct thats is usually used in the match_ep()
callback by the gadget controller driver
Change-Id: I94fe5d1b3ae984cbf3f6e10f86020191d8ca8090
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 77dcbdf3c1ce96de19c00caca0766b5bbaa0cf28)
Profiling the EHCI driver shows a significant performance problem in
ehci_submit_async(). Specifically, this function keeps enabling and
disabling async schedule back and forth for every single transaction.
However, enabling/disabling the async schedule does not take effect
immediatelly, but instead may take up to 1 mS (8 uFrames) to complete.
This impacts USB storage significantly, esp. since the recent reduction
of maximum transfer size to support more USB storage devices. This in
turn results in sharp increase in the number of ehci_submit_async()
calls. Since one USB storage BBB transfer does three such calls and
the maximum transfer size is 120 kiB, the overhead is 6 mS per 120 kiB,
which is unacceptable.
However, this overhead can be removed simply by keeping the async
schedule running. Specifically, the first transfer starts the async
schedule and then each and every subsequent transfer only adds a new
QH into that schedule, waits until the QH is completed and does NOT
disable the async schedule. The async schedule is stopped only by
shutting down the controller, which must happen before moving out
of U-Boot, otherwise the controller will corrupt memory.
Change-Id: I33a5eccac2579be09c5f1c9385ae245e680bc125
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 02b0e1a36c5bc20174299312556ec4e266872bd6)
Calling cache flush on invalid buffer, even with zero length might cause
an exception on certain platforms.
Change-Id: Idf8e2c87a24c80627279faa69430881d5c2c6800
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit fd15b58c1a9a61edcdeef8ce1eb4df2442295f58)
This is needed to make Windows THOR flash tool happy, because it
starts sending data only when interrupt packet is received on the 3rd
endpoint.
Change-Id: I51b9eee20646a7a0f65a1282fe96a575d3ebead7
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit ade08db8993687926773b32a477d9a24a9ede9e7)
Some boards don't populate clk/reset entries as these are are optional
as per binding documentation. Therefore, don't fail driver probe if
clk/reset entries are absent in DT.
This fixes fastboot failures seen due to enabling of CONFIG_CLK on AM57xx
Change-Id: I5a8e1d24f74b78647fd263ba11eaf68d4252abb5
Fixes: e8e683d33b0c ("board: ti: am57xx-idk: Configure the CDCE913 clock synthesizer")
Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit d624434f5ebc5e3eb5f5609f06200f477cf8d8b5)
The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
to work.
This patch only supports OTG0 with UTMI PHY.
Change-Id: Iccbcd113f87e5382eab12558abbb7ff596e4688d
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 235f5e158e336371759f98ffbf265fe078cda251)
This fixes the issues with calculation of controller indexes in
ehci_usb_bind() for iMX7, as USB controllers on iMX7 SoCs aren't
placed next to each other, and their addresses incremented by 0x10000.
Example of USB nodes for iMX7S/D:
usbotg1: usb@30b10000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b10000 0x200>;
^^^^^^^^^^
....
usbotg2: usb@30b20000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b20000 0x200>;
^^^^^^^^^^
....
usbh: usb@30b30000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b30000 0x200>;
^^^^^^^^^^
....
Which was leading to usb enumeration issues:
Colibri iMX7 # usb start
starting USB...
Bus usb@30b10000: USB EHCI 1.00
Bus usb@30b20000: probe failed, error -22
scanning bus usb@30b10000 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
Change-Id: I2c458dfa9e590ba054f63bb1e7ce1fad525eb56c
Fixes: 501547cec1("usb: ehci-mx6: Fix bus enumeration for DM case")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1198a104d37b10064cd90f36d472787d549eda02)
Add a new function that read quirk and configuration information from the
DT. The goal is to allow platforms using their own version of DWC3 driver
to migrate to the generic DWC3 driver.
The function is adapted from the function dwc3_get_properties() in the
linux dwc3 driver introduced in commit c5ac6116db35d.
Change-Id: I0716519c36b390cee532d3556e136012a277d036
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit ba6c5f7a28c8f8ac9eae194c2d37afa0ef51cb3d)
There is no need to fail if the maximum speed is not specified.
If the speed is not specified, do the same as linux and assume super speed.
Change-Id: I6fd5df9a3536a939b96915f6e260904da947e466
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1a63e5e5fbfff7779ce24b404bef3b8ccddf1a8b)
Currently the host driver used by dwc3-generic is "xhci-dwc3". This is
a functional driver but it doesn't use the dwc3 core and, in particular,
it lacks some bits that may be important.
For example on the k2 platforms, it is important that the phy are properly
suspended when the USB is not used anymore. The dwc3 core also has a
partial support for quirks.
The new driver can be used as a drop-in replacement for "xhci-dwc3".
In terms of implementation, it may seem strange that 2 private structures
dwc3_generic_host_priv and dwc3_generic_priv) are used. The reason for this
is simply that the xhci layer expects a struct xhci_ctrl at the beginning
of the private data and it seemed wasteful to include it also for the
peripheral case.
Change-Id: I68b9e506836292d5de24feb55c5619d907c173ef
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit b575e909168ca559609f6793720c4811b1dd55fd)
Factor code for re-usability.
This is another step toward adding host support.
Change-Id: I7c59c13bd9df4839e77555a45720fe318acde94c
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1af590df164f88fffb6484842eec8c8d8e500e70)
Separate platform data from the private data.
This is one step toward adding host support.
Change-Id: Ibd70d22283d064c77a179105c7e7f5675a598c49
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 3a38a0adb95bfebbbd39b2bb164f04bdeb10bc03)
No one is actually implementing those functions.
We could remove calls to these altogether, but it does not really hurt to
keep the empty inlined version at the moment and it satisfies a symmetry
with the gadget mode.
Change-Id: Icad0b0babdda6150088d722984b03d9cdf5c368b
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 33a99b43651b58fbb10f3778a16dd4c0a4db9708)
The xhci.h header file is currently located under drivers/usb/xhci
Move it to the include/usb folder to make it available to drivers that
are not under drivers/usb/xhci
Change-Id: I13705562893b30327708fbc321547bac79615785
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1708a12377b98397606677e117f93f07d7cd2f7e)
This allow the phy to enter idle and then suspend.
the K2 platforms require the PHY to be suspended before the USB domain
clock can be turned off.
Change-Id: Id674a95ff3cacb9e614cdc583f4a755e8301b7d7
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit bbe3d4a6c14e17d251029e4dde07f184244e9a4a)
This driver is not used anymore.
Conflicts:
configs/avnet_ultra96_rev1_defconfig
configs/xilinx_zynqmp_zcu100_revC_defconfig
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
configs/xilinx_zynqmp_zcu104_revA_defconfig
configs/xilinx_zynqmp_zcu104_revC_defconfig
configs/xilinx_zynqmp_zcu106_revA_defconfig
configs/xilinx_zynqmp_zcu111_revA_defconfig
drivers/usb/host/Kconfig
drivers/usb/host/xhci-zynqmp.c
Change-Id: I1faf3a98a74132ca2b2ba8b35931dee2c5bd5822
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit a8973731a452323e8767e8f9775c7d06921ebed5)
Phy setup should be done before dwc3 soft core reset as it is done
in linux & this fixes unreliable detection of usb cable on host side.
Change-Id: I4e49d99544d0cd4a6c4215652b9ca328d29ce24c
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1a031d236a9eeb28ced5438242987ae6a45f3054)
Some clock driver do not have a clk_enable() call back, and we should not
treat this as fail in ehci probe like other modules, eg. clk_enabl_bulk()
do not return fail if ret value is '-ENOSYS'
Change-Id: I6a87df188857287f860d4c7d9e66694e561da2dd
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
(cherry picked from commit 6578db896113816e5b61d1914169fad5f06d7903)
Some clock driver do not have a clk_enable() call back, and we should not
treat this as fail in ehci probe like other modules, eg. clk_enabl_bulk()
do not return fail if ret value is '-ENOSYS'
Change-Id: I4686a87238ff5dff7a8f1c2e4df03cce4581aa0b
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
(cherry picked from commit 54a0c7b2e7a233aa3975771592afb8e0e2f6acc0)
commit 65c1f9820c8f79f "usb: Add nonblock argument to submit_int_msg"
breaks the musb_hcd driver.
Fixing it by adding the missing argument
Change-Id: I54ead50fdf48f1936caca65e64a61486745f4723
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit e3e5825d0143c2b24583d256ef111ae9344382a2)
An USB 1.1 keyboard connected to dwc2 through a high-speed hub does not
report status until it changes. With this patch you can enable keyboard
by pressing a key while USB devices are probed. Without a keypress no
state is reported and the probe times out. We don't want to wait for a
keypress or timeout while polling for keypresses so implement an int_msg
nonblock variant that exits early on error.
Change-Id: I6d89952ca5c00a1b076ae3fe9d9632ebdc6af843
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 9dcab2c4d2cb50ab1864c818b82a72393c160236)
This will be used to implement non-blocking keyboard polling in case of
errors.
Conflicts:
common/usb.c
common/usb_kbd.c
common/usb_storage.c
include/usb.h
Change-Id: I4a951d779e2cf9e80380f93000a87a617453fb32
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 3437121c037f502a3b0faaec97059777034a1ead)
This quirk is necessary for the Amlogic GXL SoCs otherwise the
Port 2 PHY doesn't get out of suspend and U-Boot resets the board after:
XHCI timeout on event type 33... cannot recover.
BUG: failure at drivers/usb/host/xhci-ring.c:474/xhci_wait_for_event()!
BUG!
This quirk is also handled in the dwc3 core code, but until the
xhci-dwc3 driver uses the dwc3 core, the quirk must be handled here
to fix USB support on the Amlogic libretech-cc and libretech-ac board
when a device is only plugged in the OTG port.
Change-Id: Iba72fb52411856785b6bd6ed829e1585ba00bebe
Cc: Yuri Frolov <crashing.kernel@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Fixes: dc9cdf859e ("usb: dwc3: Add DWC3 controller driver support")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit b35b8076828d1059c1fcc648ed8c8210ebe6a3dd)
Add DM regulator support for toggling VBUS, this is useful on boards
which control the VBUS e.g. through GPIO.
Change-Id: I0f6e296d34613ada8d7e96a8ec86a4288614822c
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 769a9cd4bbd7ae9b8170b3dd6ba54b84fde59224)
Fix remaining checkpatch complaints in the driver.
Change-Id: Ic58362d2e4a9a6a560ceb5c12fbfb502b814ad6f
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 8b5483015496100b3f5a790a58cc3019815654e0)
Add missing Kconfig entry for the R8A66597 driver.
Change-Id: I8f476bc44995b1aaf296a3b9105e8e2d42876c20
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit a3d65651d9dd1b65722c21bf739d1e9978320a47)
Convert the R8A66597 USB driver to DM and add support for DT probing.
Drop support for legacy non-DM and non-DT probing, since there are no
platform using that.
Change-Id: Ic4a15ca6cdbea7782257b37683a62a971f4902bc
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 7f3858f90d01cca631d7c6b40301618af060acd7)
While the USB controller can work both in LE and BE modes, there is
no user for the BE mode, so drop it. If there ever is a user for it,
it can be easily re-added back.
Change-Id: Icbafe9f751113a669c5322af618bcc27bf20ac75
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 81644e01c02967edd3da7eb6c776478a34fa7370)
Replace in{bwl}()/out{bwl}() IO accessors with read{bwl}()/write{bwl}(),
to make the driver compile both on SH and ARM.
Change-Id: I5fc72a93b162d7473a3717a07bfdcd88fe455ec5
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 4c9a135715ad80ec10a9e642d35e3bbf1535fe56)
No other platforms use this r8a66597 controller but RZ/A1,
make RZ/A1 support the default and drop all the other SoC
support to remove ifdeffery.
Change-Id: I15bd3497d23c34c6cd43c849f09ec3904ec898da
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 3ff134b7f1c06f8482ef8ab296d5a89743d219db)
Remove CONFIG_SUPERH_ON_CHIP_R8A66597 macro, which is unused.
Change-Id: I27a8ff1b6487ebc2db6ce50fa2b034030e84f156
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 0b80f212824f632f1acb0d74fd932c05a0262fc3)
dfu_prepare_function() allocates N+1 descriptor header structures,
the last one being the "DFU Functional Descriptor".
dfu_unbind() handles de-allocation, but fails to free the final
one (eg. "DFU Functional Descriptor"), leading to memory leak.
Fixed by incrementing counter, as in dfu_prepare_function().
Change-Id: I990f3874d6e3dca78036d6f30a05e765fbe38c67
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit fe876984a428cc0058bdb536ac948397762f3c0d)
add new DM based PCI driver ohci-pci for PCI-based
OHCI USB support.
Change-Id: Ie3cb7e552e48eb100cdfc2f7807136297b5563cb
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 991e66017ccd79cf4b89a729433a9606a771bd2b)
Change-Id: I7e7a39a7d3ff257381a63a6bc07f86d1fa16a159
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit f9c7fecbeb938d9a17e31bf7c8766190752790ae)
set OHCI_USE_NPS if DM_PCI is enabled.
Change-Id: I75001b7d3c9efdcd448d089ee0e99019a35d9d31
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit dc4e48d845d9971d2b21f99c12f874dd06cedc0a)
commit 57faca19a8 ("drivers: USB: OHCI: allow compilation for 64-bit targets")
broke ohci support for the mpc85xx based socrates board,
as it removed volatile keyword from ohci_readl/writel.
Fix this so usb works again on socrates board.
Change-Id: I558791c276aa1641dd735b825ba93f8da8ed0830
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit a5a7486e62b0aa4afa1fe1a3b30f7dd682eb1ff8)
var ohci_pci_ids is only used if DM_USB is not enabled.
So define this varaible only if
!CONFIG_IS_ENABLED(DM_USB)
Change-Id: I2da8e2b51cd2f225e7b452bf5bb0179a2d1e4ee4
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit b005d7d5f96539450e50450f12491913e135c2a9)
With the recently added phy driver, this patch will enable the
musb driver on the da8xx to operate in host mode.
Change-Id: I31da15be4324f43429fddf31323ff9fc648425ae
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 5608331d813630120871d04847b59628ec59f7f9)
Configure USB2 PHY register based on "phy_type" property and
handle all the quirks that are relevant for Rockchip RK3399 SoCs.
Change-Id: Idac50a031e8e924712fef8ad61a622f8e85f3e86
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 062790f461312f1b954ae876f85da8f6ce5fcc73)
dwc3-generic has been broken since MISC uclass has been modified to scan DT
sub-nodes after bind.
Fixing it by a using the no-op uclass.
Change-Id: Id95c49a16951cbe8bc7e58d8a3f85a7372ffd00a
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 3b83829ed63fabe460592395571c1d8fd9b861c8)
There is simply no reason to do that here.
Change-Id: I4336f493dc638bd0b5dd57cbd4a934c93c5bb0ff
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit e445d46651de61fdfecf34cc2cd97d58ca6c5cf3)
The EHCI iMX6 driver is only partly converted to DT probing and
still uses a tremendous amount of hard-coded addresses. Worse,
the driver uses hard-coded SoC-model-specific base addresses, which
are derived from values protected by SoC-specific macros, hence the
driver is also compiled for a specific SoC model. Even worse, the
driver depends on specific sequential indexing of the controllers,
from which it derives offsets in the PHY and ANATOP register sets.
However, when the driver is probed from DT, the indexing is not
correct. In fact, each controller has index 0. This patch derives
the index for DT probing case from the controller base addresses,
which is not the way this should be done, however it is the least
intrusive approach, favorable this close to release.
The necessary steps to convert this driver fully to DT probing are
described inside the patch, however this should be done in the next
release and depends on iMX clock driver patches.
Change-Id: I81cef54d5e6f1bab2aef407ad053b5af3cd4e94f
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Ludwig Zenz <lzenz@dh-electronics.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 501547cec1f7f0438cae388a104ff60f18576c01)
Add support for loading u-boot FIT images over the USB SDP protocol in
the SPL
Change-Id: I41461b58c088a10eca6e48b0d49c76944c37c3fa
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
[Various build fixes]
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 2c72ead7387404eba16c556d2f204c52c36c27f9)
Allow device mode in DWC2 driver when device tree select the dr_mode
"peripheral" or "otg".
The device mode is not allowed when dr_mode = "host" in device tree.
Change-Id: Iede854cdf940f5e1ef14a7e394087ac97998213a
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 7c654683464dc4cd89f9a8198e26336263390b57)
Manage g-tx-fifo-size as a array as specify in the binding.
Change-Id: Ie2f0fa8eda62d762fe79072db377c1b00b23ee4c
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 7350a75b517b6162c8f832a9ead09b9e26e8068f)
adopt 32 bit addr in fsl_esdhc for CONFIG_PPC.
So adopt 32 bit address for CONFIG_PPC.
Change-Id: Ibb69849ed19fa18f494807020f9a6a911692b1aa
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit ad9f2be3348c088e7839fd3598db3b352060bff1)
Per feedback from Marek, he suggested better handling and
to enable DM_FLAG_OS_PREPARE, this patch re-orders some of
the error checking, and errors returns the error code right
away and also sets DM_FLAG_OS_PREPARE.
Change-Id: I639a5e4f6d5c89a18e722db2601cf18acb96cbb3
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 3a90b50a32b6b8a2d66dc10c19e3c15d5bd1a092)
Adds support for Amlogic G12A USB Control Glue HW.
The Amlogic G12A SoC Family embeds 2 USB Controllers :
- a DWC3 IP configured as Host for USB2 and USB3
- a DWC2 IP configured as Peripheral USB2 Only
A glue connects these both controllers to 2 USB2 PHYs, and optionnally
to an USB3+PCIE Combo PHY shared with the PCIE controller.
The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including
routing of the OTG PHY between the DWC3 and DWC2 controllers, and
setups the on-chip OTG mode selection for this PHY.
This driver sets the OTG capable port as Host mode by default,
the switch to Device mode is to be done in a separate patch.
Change-Id: I099bb5fbda0fdd52c4d78e32f879f8324bda4c59
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit adb049abf7a209629c7b5e4bc673a0d802c616c2)
Vignesh Raghavendra
Sherry Sun
Marek Vasut
Marek Szyprowski
Ye Li
Igor Opaniuk
Jean-Jacques Hiblot
T Karthik Reddy
Kever Yang
Michal Suchanek
Neil Armstrong
Ralph Siemsen
Heiko Schocher
Adam Ford
Mark Kettenis
Marek Vasut
Frieder Schrempf
Patrick Delaunay
Yinbo Zhu