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8 Commits

Author SHA1 Message Date
Joseph Chen 58d85a144d armv8: dump SP content when system crash 
Change-Id: I8f1d068f10eddf467413fb459934b1cb85481bb0
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2018-09-20 11:03:44 +08:00
Joseph Chen 24cd8f3602 armv8: dump registers when system crash 
default provide: grf, pmugrf, cru and pmucru, it looks like:

rockchip,px30-cru:
ff2b0000:  0000304b 00001441 00000001 00000007
ff2b0010:  00007f00 00000000 00000000 00000000
ff2b0020:  00003053 00001441 00000001 00000007
......

rockchip,px30-grf:
ff140000:  00002222 00002222 00002222 00001111
ff140010:  00000000 00000000 00002200 00000033
ff140020:  00000000 00000000 00000000 00000202
......

Change-Id: I1630b07cb9412103b737ac4c2f6d86cfe3c81fc1
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2018-07-18 16:33:02 +08:00
Joseph Chen faa7eb0f76 armv8: exceptions: optimize exception regs info 
Add arm core registers bits description, it looks like:

Relocate offset = 000000003db55000
* ELR(PC)    =   000000000025bd78
* LR         =   000000000025def4
* SP         =   0000000039d4a6b0

* ESR_EL2    =   0000000040732550
        EC[31:26] == 001100, Exception from an MCRR or MRRC access
        IL[25] == 0, 16-bit instruction trapped

* DAIF       =   00000000000003c0
        D[9] == 1, DBG masked
        A[8] == 1, ABORT masked
        I[7] == 1, IRQ masked
        F[6] == 1, FIQ masked

* SPSR_EL2   =   0000000080000349
        D[9] == 1, DBG masked
        A[8] == 1, ABORT masked
        I[7] == 0, IRQ not masked
        F[6] == 1, FIQ masked
        M[4] == 0, Exception taken from AArch64
        M[3:0] == 1001, EL2h

* SCTLR_EL2  =   0000000030c51835
        I[12] == 1, Icaches enabled
        C[2] == 1, Dcache enabled
        M[0] == 1, MMU enabled

* VBAR_EL2   =   000000003dd55800
* HCR_EL2    =   000000000800003a
* TTBR0_EL2  =   000000003fff0000

x0 : 00000000ff300000 x1 : 0000000054808028
x2 : 000000000000002f x3 : 00000000ff160000
x4 : 0000000039d7fe80 x5 : 000000003de24ab0
......
x28: 0000000039d81ef0 x29: 0000000039d4a910

Change-Id: I828cafc961fdc3fcb2aa08916a7e36f690627313
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2018-07-17 10:07:22 +08:00
Peng Fan 5e076729c1 arm64 :show_regs: show the address before relocation 
After relocation, when error happends, it is hard to track
ELR and LR with asm file objdumped from elf file.

So subtract the gd->reloc_off the reflect the compliation address.

Change-Id: I1db18049b1e895c74ec75ed6ce77231cf4f03bce
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 082693f4f02ad7a9de192e73feae34e28856b8e3)
 2018-01-17 15:27:28 +08:00
Kever Yang f4fc5f8dd3 arm: irq: do not enable irq in SPL/TPL 
Change-Id: I6a9b8b883ede2e45e2c5760c633f04bd9ab4fe4e
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2017-11-09 19:34:04 -08:00
Joseph Chen fa40f8a0c4 ARM: add support for irq interrup framework 
both GICV2 and GICV3 are supported

Change-Id: Ie928cc781c0e0830b98d12c4033e45a43befc2ff
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2017-09-27 10:34:43 +08:00
Alexander Graf 649829157e arm64: Allow EFI payload code to take exceptions 
There are 2 ways an EFI payload could return into u-boot:

  - Callback function
  - Exception

While in EFI payload mode, x18 is owned by the payload and may not contain
a valid pointer to gd, so we need to fix it up. We do that properly for the
payload to callback path already.

This patch also adds gd pointer restoral for the exception path.

Signed-off-by: Alexander Graf <agraf@suse.de>
 2016-03-15 21:30:11 -04:00
David Feng 0ae7653128 arm64: core support 
Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>

Signed-off-by: David Feng <fenghua@phytium.com.cn>
 2014-01-09 16:08:44 +01:00