NAND flavors, like serial and parallel, have a lot in common and would
benefit to share code. Let's move raw (parallel) NAND specific code in a
raw/ subdirectory, to ease the addition of a core file in nand/ and the
introduction of a spi/ subdirectory specific to SPI NANDs.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Change-Id: Ibb56f85620c4798fb579be3e4e30438963b7c48b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a430fa06a4ac50e785fdbfb7f43c3cb14b35619c)
There is no reason to have NAND, SPI flashes and UBI sections outside of
the MTD submenu in Kconfig.
Change-Id: I1c42acb7aa7c359d20edff6452e45331ceadea07
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ce9bdc87436ef91129876c9b16fcf5111eea69aa)
Some helpers might be useful in a future 'mtd' U-Boot command to parse
MTD device list.
Change-Id: I127b2a919e781c749271caa8d2186a69edb70982
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d02f1d36ec6fe6bfadd77fa71b1df228010ddaa8)
Some MTD sublayers/drivers are implementing ->_read/write() and
not ->_read/write_oob().
While for NAND devices both are usually valid, for NOR devices, using
the _oob variant has no real meaning. But, as the MTD layer is supposed
to hide as much as possible the flash complexity to the user, there is
no reason to error out while it is just a matter of rewritting things
internally.
Add a fallback on mtd->_read() (resp. mtd->_write()) when the user calls
mtd_read_oob() (resp. mtd_write_oob()) while mtd->_read_oob() (resp.
mtd->_write_oob) is not implemented. There is already a fallback on the
_oob variant if the former is used.
Change-Id: Ic8f4749900a2034cfaa103effcdace78242bcbe7
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ca040d8512f4d93a7eb83f7b8fec8f4b8b1d3192)
Unlike what's done in mtd_read/write(), there are no checks to make sure
the parameters passed to mtd_read/write_oob() are consistent, which
forces implementers of ->_read/write_oob() to do it, which in turn leads
to code duplication and possibly errors in the logic.
Do general sanity checks, like ops fields consistency and range checking.
Change-Id: Ibe2de07dfd3d7504d615b1c22cdcb34c79eca63e
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Peter Pan <peterpandong@micron.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
[Miquel: squashed the fix about the chip's size check]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8fad769f1eab88a2bcf0b714694158968f58715a)
There's no reason for having mtd_write_oob inlined in mtd.h header.
Move it to mtdcore.c where it belongs.
Change-Id: I1e06b151912689171ff9c66f95cba13f256d27a1
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5f50d82d8918b711717b4bbd96c6f348eb6e2a2c)
Some MTD sublayers/drivers are implementing ->_read/write_oob() and
provide dummy wrappers for their ->_read/write() implementations.
Let the core handle this case instead of duplicating the logic.
Change-Id: I7276effeba2885da48ab4834e272c51a258588dd
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 596cf083da34c2007f8ec760c8b077f6f28ee655)
add delay before processing the status flags in pxa3xx_nand_irq().
Change-Id: I06cb7459b9f1127ce8d66b04fdaedc026b4c77da
Signed-off-by: David Sniatkiwicz <davidsn@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
c: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e76afd84095a10e7cd9d8ee6b74ed94941e5f4f8)
Add support for NAND chips with 8KB page, 4 and 8 bit ECC (ONFI).
Change-Id: I9fbcd1b11f5ef22d352730b44be5f84cacc255aa
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b7b3f2c8bbf346b29f877b61d7e2b12a877b01d0)
Add comments with timing parameter names and some details about
nand layout fileds.
Remove unneeded definition.
Change-Id: I82d550b47e92bf0ec3c4aaadd6bd0a537fb96ce5
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e9a0777f851c3ffa5ece59921427d89bab1d7506)
Replace the hardcoded value of page chink with value that
depends on flash page size and ECC strength.
This fixes nand access errors for 2K page flashes with 8-bit ECC.
Move the initial flash commannd function assignment past the ECC
structures initialization for eliminating usage of hardcoded page
chunk size value.
Change-Id: I3d75d6b65012ca38572d75e505bb085b643830d6
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2057eb0b163ac31fee00ae6ef9e8e27dcca65fd5)
Add timings and device ID for Toshiba TC58NVG1S3HTA00 flash
Change-Id: I7aa6eb7f84b5063e5497355058cbe3bc00519f2a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b0d7c106c9703498f12bb1254b02574c803874a0)
Add support for 2KB page 8-bit ECC strength flash layout
Change-Id: I3a4f2712c7107be83d2c63adc2c62841f4dac56d
Signed-off-by: Victor Axelrod <victora@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ac56a3b30cc74f2c9dd667705e756ff5f5aeda0f)
In the current driver, OOB bytes are accessed in raw mode, and when a
page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the
driver must read the whole spare area (64 bytes in case of a 2k page,
16 bytes for a 512 page). The driver was only reading the free OOB
bytes, which was leaving some unread data in the FIFO and was somehow
leading to a timeout.
We could patch the driver to read ->spare_size + ->ecc_size instead of
just ->spare_size when READOOB is requested, but we'd better make
in-band and OOB accesses consistent.
Since the driver is always accessing in-band data in non-raw mode (with
the ECC engine enabled), we should also access OOB data in this mode.
That's particularly useful when using the BCH engine because in this
mode the free OOB bytes are also ECC protected.
Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support")
Cc: stable@vger.kernel.org
Change-Id: I4b53b3f4fd84e58ca78d01492a3768ba5ba4eaa0
Reported-by: Sean Nyekjær <sean.nyekjaer@prevas.dk>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Tested-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f3d235702de09622a542ba2830882d23e2dfee1f)
This commit is needed to properly support the 8-bits ECC configuration
with 4KB pages.
When pages larger than 2 KB are used on platforms using the PXA3xx
NAND controller, the reading/programming operations need to be split
in chunks of 2 KBs or less because the controller FIFO is limited to
about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to
this requirement, the data layout on NAND is a bit strange, with ECC
interleaved with data, at the end of each chunk.
When a 4-bits ECC configuration is used with 4 KB pages, the physical
data layout on the NAND looks like this:
| 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC |
So the data chunks have an equal size, 2080 bytes for each chunk,
which the driver supports properly.
When a 8-bits ECC configuration is used with 4KB pages, the physical
data layout on the NAND looks like this:
| 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC |
So, the spare area is stored in its own chunk, which has a different
size than the other chunks. Since OOB is not used by UBIFS, the initial
implementation of the driver has chosen to not support reading this
additional "spare" chunk of data.
Unfortunately, Marvell has chosen to store the BBT signature in the
OOB area. Therefore, if the driver doesn't read this spare area, Linux
has no way of finding the BBT. It thinks there is no BBT, and rewrites
one, which U-Boot does not recognize, causing compatibility problems
between the bootloader and the kernel in terms of NAND usage.
To fix this, this commit implements the support for reading a partial
last chunk. This support is currently only useful for the case of 8
bits ECC with 4 KB pages, but it will be useful in the future to
enable other configurations such as 12 bits and 16 bits ECC with 4 KB
pages, or 8 bits ECC with 8 KB pages, etc. All those configurations
have a "last" chunk that doesn't have the same size as the other
chunks.
In order to implement reading of the last chunk, this commit:
- Adds a number of new fields to the pxa3xx_nand_info to describe how
many full chunks and how many chunks we have, the size of full
chunks and partial chunks, both in terms of data area and spare
area.
- Fills in the step_chunk_size and step_spare_size variables to
describe how much data and spare should be read/written for the
current read/program step.
- Reworks the state machine to accommodate doing the additional read
or program step when a last partial chunk is used.
This commit is taken from Linux:
'commit c2cdace755b'
("mtd: nand: pxa3xx_nand: add support for partial chunks")
Change-Id: I63a98c133cbadb1cfe1b1919bf08182e5ea99c47
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b47f677931b2255d0d454e100590e94f0dd97f55)
This commit simplifies the initial configuration performed
by pxa3xx_nand_scan. No functionality change is intended.
This commit is taken from Linux:
'commit 154f50fbde53'
("mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan")
Change-Id: I72a34c2a18addb5a96b98fa5799bc9391a934d26
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 7efd95eacf790714e70415cbe290056fedc33f82)
The Data Flash Control Register (NDCR) contains two types
of parameters: those that are needed for device identification,
and those that can only be set after device identification.
Therefore, the driver can't set them all at once and instead
needs to configure the first group before nand_scan_ident()
and the second group later.
Let's split pxa3xx_nand_config in two halves, and set the
parameters that depend on the device geometry once this is known.
This commit is taken from Linux:
'commit 66e8e47eae65'
("mtd: pxa3xx_nand: Fix initial controller configuration")
Change-Id: I1be50c463d38627c0ed43258c59ca9624d56912e
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b87ae6f587e44e3974e41bd80dbc628540211604)
The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transferred data.
However, the initial chunk size is used in a non-split way,
during device identification. Therefore, it must be large enough
for all the NAND commands issued during device identification.
This includes NAND_CMD_PARAM which was recently changed to
transfer up to 2048 bytes (for the redundant parameter pages).
Thus, the initial chunk size should be 2048 as well.
On Armada 370/XP platforms (NFCv2) booted without the keep-config
devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM
command:
[..]
pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device
pxa3xx-nand f10d0000.nand: Wait time out!!!
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38
nand: Micron MT29F8G08ABABAWP
nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224
This commit is taken from Linux:
'commit c7f00c29aa8'
("mtd: pxa3xx_nand: Increase the initial chunk size")
Change-Id: I7bcf3042a0567171d0dc0a90bf3d15c821914cd1
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6bbe7f681feac91fc03a4dc2e88bc0d9391bfaa8)
The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit sets the hardware
maximum read ID count, which should be more than enough on all cases.
Also, we get rid of the read_id_bytes, and use a macro instead.
This commit is taken from Linux:
'commit b226eca2088'
("nand: pxa3xx: Increase READ_ID buffer and make the size static")
Change-Id: If5d3398463cb409d7b62f9d7f23dd29ea77efe7a
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 94488612cb21e51b772e3b616c8f1acfe2d0961c)
When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase
This patch is taken from Linux:
'commit 21fc0ef9652f'
("mtd: nand: pxa3xx-nand: fix random command timeouts")
Change-Id: I399aaaacff8259bd282c924e0b8471aa8d32d252
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit cd11b2b457bb8aa5e0e72c4d90df1c7995c738b4)
When the nand is first probe, and upon the first command start, the
status bits should be cleared before the interrupts are unmasked.
This commit is taken from Linux:
'commit 0b14392db2e'
("mtd: nand: pxa3xx_nand: fix early spurious interrupt")
Change-Id: Ie6b9b9dc2983df500b1496d814fa957c53ce4321
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 658999244a0446a32301bc34c8fa53f1a3f05594)
Since the pxa3xx_nand driver was added there has been a discrepancy in
pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min.
This brings us into line with the current Linux code.
Change-Id: I67ac39aca2dccf8463c3d5404b9abb4f2b59d593
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d3859d1b5349e8105b23043e6e7158e3dc1582d4)
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the
one that is already part of struct nand_chip. This brings us in line
with current U-boot and Linux conventions.
Change-Id: Ida9c1652736c94db9cebd295d32aed034e868660
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8cdcf672c59b778f2a68a4f5d6c5f4d584f7ef54)
The initial buffer is used for the initial commands used to detect
a flash device (STATUS, READID and PARAM).
ONFI param page is 256 bytes, and there are three redundant copies
to be read. JEDEC param page is 512 bytes, and there are also three
redundant copies to be read. Hence this buffer should be at least
512 x 3. This commits rounds the buffer size to 2048.
This commit is taken from Linux:
'commit c16340973fcb64614' ("nand: pxa3xx: Increase initial buffer size")
Change-Id: I61c33092402a06ab75b390b791ba4cc57072de3b
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 144532242ed3588bf63acccc6a46399b87861c03)
If the OOB size is not multiple of the cache line size, the ARMv7
cache operation still prints "Misaligned operation at range".
=> nand info
Device 0: nand0, sector size 256 KiB
Page size 4096 b
OOB size 224 b
Erase size 262144 b
subpagesize 4096 b
options 0x00104200
bbt options 0x00060000
=> nand dump 0
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
CACHE: Misaligned operation at range [9fb15280, 9fb16360]
...
The cache flushing operations won't happen in this case to cover all of
the range to fix this by making sure we have things aligned.
Change-Id: I8c396d3c8f00bca5d82840c71caa685c0e912cb9
Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Reword the commit message to be clear this is a direct problem
rather than just a warning]
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e8f65763ef07e0667f57dda7eece657f8fe136a7)
This is a fix made for the fsl_ifc_nand driver on linux kernel by
Pavel Machek and is applied to uboot. It is currently on applied on
linux-mtd.
https://patchwork.kernel.org/patch/9758117/
IFC always raises ECC errors on erased pages. It is only ignored when
the buffer is checked for all 0xFF by is_blank(). The problem is a
single bitflip will cause is_blank() and then mtd_read to fail. The fix
makes use of nand_check_erased_ecc_chunk() to check for empty pages
instead of is_blank(). This also makes sure that reads are made at ECC
page size granularity to get a proper bitflip count. If the number of
bitflips does not exceed the ECC strength, the page is considered empty
and the bitflips will be corrected when data is sent to the higher
layers (e.g. ubi).
Change-Id: Iff78706ceb288d52ad82343d67eb1bec3275ed03
Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz>
Cc: Pavel Machek <pavel@denx.de>
Cc: Scott Wood <oss@buserror.net>
Acked-by: Pavel Machek <pavel@denx.de>
[Kurt: Replaced dev_err by printf due to compiler warnings]
Tested-by: Kurt Kanzenbach <kurt@linutronix.de>
Signed-off-by: Kurt Kanzenbach <kurt@linutronix.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 1711add3dca291376072ec0c66b01023a3462daf)
Add ISSI to Kconfig to make it selectable via menuconfig.
Also convert all current platforms.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I623a8e29359455055f7d20ad60bb8972846bec6e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 13f451bf5625e222e881779e69d92a2002e41dfc)
Add support for SPANSION s25fl128l
Change-Id: I52bc8fe66c45a196bc688c1eb5a55af322ea0b52
Signed-off-by: Clément Laigle <c.laigle@catie.fr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: fixed , at the end of } ]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 04d57b1d588aeda00f308028aad6239467f24923)
Return the error code of the set_features function only if
the error code is not ENOTSUPP. Otherwise, if this function
is not supported, it will return and fail to initialize the
NAND.
Change-Id: I8fc8c50831fa8c078cb503fd6d2cd9bf9f1032bc
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 850bdafa503e2045a8e931ce601fd71dc33157cf)
Convert the EINVAL error into ENOTSUPP when the GET/SET_FEATURES
is not supported.
Change-Id: I97f0329262a75602fd2d776a925ff804d991f45a
Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit cbe9ea26e3a275bc3e47414797406a234c0baa55)
The NAND framework makes sure to pass in the buffer with at least
chip->buf_align alignment. Currently, the Denali NAND driver only
requests 16 byte alignment. This causes unaligned cache operations
for the DMA transfer.
[Error Example]
=> nand read 81000010 0 1000
NAND read: device 0 offset 0x0, size 0x1000
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
CACHE: Misaligned operation at range [81000010, 81001010]
4096 bytes read: OK
Change-Id: I2e336f50ce2cf91e6e0532152ea7a153685f60b4
Reported-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4a610fada193057c97c1b23016ef119f98459b22)
Support i.MX 6 NAND GPMI driver data from device tree.
Change-Id: Ib374f5e929971be8e9bdad6948ef9908e25e47cf
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c7f367bc8d6b1b5da79aa430c4449c9f505b9577)
This converts the following to Kconfig:
CONFIG_MTD_PARTITIONS
CONFIG_MTD_DEVICE
Signed-off-by: Adam Ford <aford173@gmail.com>
Change-Id: I90c45c7716965009c00d18a19f5491f19b1ab8b3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9c5b00973bceb7c0192bd6b03672d69b092700b4)
This converts the following to Kconfig:
CONFIG_NAND_DAVINCI
Signed-off-by: Adam Ford <aford173@gmail.com>
Change-Id: I3d95031ee5ebaa5e8ac6c03236622089ccf3caee
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit eba7f1ff6c9836931f0ce2812182190862e38b5f)
This converts the following to Kconfig:
CONFIG_NAND_ATMEL
Signed-off-by: Adam Ford <aford173@gmail.com>
Change-Id: Ic71bd0ef5704faf04852bf51d265d94e1a8dc259
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e7db856bf96213ba3f6b716be9fa264e184f74e2)
This converts the following to Kconfig:
CONFIG_NAND_LPC32XX_SLC
Change-Id: Ib4d42bc173665d6483af8c1007006dd0422d5a86
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d294335e5d51aa83b6dd57db85c3251e9a92349e)
This commit adds paired dev info for winbond w25q16jv
(tested w25q16jvssiq with a i.mx6 board)
Change-Id: I71adbc8b57960d6c4f1f9a0d45a1b5f92cc72f43
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 51b2411946e5f247f26fde41a7227a002270d376)
Add support for the Macronix mx25l1633e nor flash. (Tested on a imx6 board)
Change-Id: If15d3a6fcf78a95c798966b720329d697bcb1bbd
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 70cff76c38a7051992e399f35e1571f24efbfded)
Add support for the Gigadevice gd25q16c nor flash. (Tested on a imx6 board)
Change-Id: I7382793b94bbe142346dfdd601bbd3f5d77e20e6
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b1360e2fc9b45650e1744138702dc6938962d608)
This commit adds the following flashes to the id-table
- W25Q16JV
- W25Q32JV
- W25Q64JV
- W25Q128JV
- W25Q256JV
Change-Id: Ic5873a7292d9b706b2839feb84c171d8cb1f5c73
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 760b75564fdf2fe53d8c4069a6fb3320586eb662)
Update the parameters sandbox_sf_bind_emul to support livetree.
Change-Id: Iec83b813c8cddd750f7061d697304fa05556c5fb
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 008dcddf9937bd2576f98b48eb5bf0f60ad36014)
The N25Q256(A) datasheet clearly states that this device does have
a Flag Status Register and does update FSR PEC bit 7 during Program
and Erase cycles to indicate the cycle is in progress. Enable the
FSR PEC bit polling on this device to prevent data corruption.
Change-Id: I3f2a50091513a52b9bc02c44d4a37f0bd6c8e392
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 069b746ad9e66ab75973020f992e059c06cf3a7c)
For now, the existing SPL MXS NAND driver only supports to identify
ONFi-compliant NAND chips. In order to allow identifying
non-ONFi-compliant chips add `mxs_flash_full_ident()` which uses the
`nand_get_flash_type()` functionality from `nand_base.c` to lookup
for supported NAND chips in the chip ID list.
For compatibility reason the full identification support is only
available if the config option `CONFIG_SPL_NAND_IDENT` is enabled.
The lookup was tested on a custom i.MX6ULL board with a Toshiba
TC58NVG1S3HTAI0 NAND chip.
Change-Id: Idcf3cec142f0e7e326c532d86e6ffc2664c633d2
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4368f85359b947da7f151265d8969d6af1235357)
The existing `mxs_flash_ident()` is limited to identify ONFi compliant
NAND chips only. In order to support non-ONFi NAND chips refactor the
function and rename it to `mxs_flash_onfi_ident()`.
A follow-up patch will add `mxs_flash_full_ident()` which allows to use
the chip ID list to lookup for supported NAND flashs.
Change-Id: I560d7f7729f0977d8a638079a849cb1c8c5d31b8
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f3f2af3bdf2af89d0621aa0fbd94a918e4447081)
Add the config option `CONFIG_SPL_NAND_IDENT` for using the NAND chip ID list
to identify the NAND flash in SPL.
Change-Id: I4d83cb678cb52e83ddf755c0188a4f2f42fe5671
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 15e207faa0c32b587c173844936cadd7bf8dee01)
`nand_get_flash_type()` allows identification of supported NAND flashs.
The function is useful in SPL (like mxs_nand_spl.c) to lookup for a NAND
flash (which does not support ONFi) instead of using nand_simple.c and
hard-coding all required NAND parameters.
Change-Id: I469c18019d13e8e7f5105ece92c581047e751924
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit da37d096820e15b2bcdb0243da2dc01707c650f2)
Add support for specified ECC strength/size using device tree
properties nand-ecc-strength/nand-ecc-step-size.
This aligns behavior with the mainline driver, such that:
- If fsl,use-minimal-ecc is requested it will use data from
data sheet/ONFI. If this is not available the driver will fail.
- If nand-ecc-strength/nand-ecc-step-size are specified those
value will be used.
- By default maximum possible ECC strength is used
Change-Id: I981df217443c7ac9684b59df8d946a7f531bc063
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 627544506f5709bb2d14f0db66661a27cd78ec0a)
Support driver data from device tree. Also support fsl,use-minimal-ecc
similar to Linux' GPMI NAND driver.
Change-Id: I3f91a764c1bf75bdb5a51328146297a4b662141f
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f75e83bfae2bcf36197e25b8b3d539b0652b83fa)
Move structs into header file so we can use a separate compile
unit for device tree support.
Change-Id: I83cfe57d76d434fe483911f8b8b3d4dea4a4d170
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 68748340c8613877d71b444c0dffe63b536d5a5f)
Add use_minimum_ecc as struct mxs_nand_info field in preparation
for device tree support.
Change-Id: Idfda9d4b95e6091ca8a4ca1f9d0541f41d4fec95
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 502bdc6b4f52fff92d19b5072a60e8b8cbfb1c04)
Miquel Raynal
Boris Brezillon
Ezequiel Garcia
David Sniatkiwicz
Konstantin Porotchkin
Victor Axelrod
Ofer Heifetz
Masahiro Yamada
Darwin Dingel
Michal Simek
Clément Laigle
Mylène Josserand
Stefan Agner
Adam Ford
Ludwig Zenz
Hannes Schmelzer
Simon Glass
Marek Vasut
Jörg Krause