This is a debug message to know if we use kernel dtb.
We have already got this info from "DTB: rk-kernel.dtb",
so remove it.
Change-Id: I28e29e43aa818ac61c9864b94bd80ceb85fc9c3a
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Ramdisk is a compressed image and it expands after descompress, which accesses
768MB+ memory and brings "Unable to handle kernel paging request at virtual address ...".
We make a appointment that the highest memory is 512MB, it makes lmb alloc safer.
fixes: 2c6a058b7e
(rockchip: implement board_lmb_reserve())
Change-Id: I728a1fbff216194b940372713387cf171028b20b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
- preloader would pass bootdev info;
- avoid going through all the possible bootdev;
- rename devtype_num_envset() to boot_devtype_init();
Change-Id: Ia047c744dc7aca97db97664fc92473e46ba102a9
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize".
This makes lmb_alloc_base() always alloc from tail of sdram.
If we don't assign it, bi_dram[0] is used by default and it may cause
lmb_alloc_base() fail when bi_dram[0] range is small.
Change-Id: I13c2c2d6135e26e647dcfde4c173d896c800fea5
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
- pass pre-loader serial configure by rk atags;
- it depends on serial aliases to find uart port;
- enabled by CONFIG_ROCKCHIP_USING_PRELOADER_SERIAL;
Change-Id: I6723cccc5e1f3dac77203b4cc19cdac631f5133b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
actually, icache is only enabled when not define CONFIG_SKIP_LOWLEVEL_INIT,
icache/dcache had better not depend on other configures macros, so enable
them anyway.
Change-Id: Iba843ffd481a24c3b0235323253a5b423160c867
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Insure if defined CONFIG_SUPPORT_SPL but not use SPL bin,
board_debug_uart_init still have be called.
Change-Id: I2e8a7bf1cfb4e6ec4a916983eb13652afe8c8af2
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Whit kernel dtb support, we need to get rk3288 dwc2 otg
node by compatible "rockchip,rk3288_usb20_otg" rather than
"snps,dwc2", because rk3288 dwc2 otg uses rockchip legacy
dwc2 driver "dwc_otg_310".
Change-Id: Ib7b536e554776f1dd09d34d0a2ac1754df9c753e
Signed-off-by: William Wu <william.wu@rock-chips.com>
We install a timer interrupt and dump pt_regs when
the timeout event trigger. This help us to know cpu
state when system hang.
Change-Id: I91aa2322036ae83ac8b9cd299bef9b521995d85b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
1. recoganize RK3288w according to HDMI Revision ID;
2. proive a weak board_fdt_fixup() as common fixup place;
3. move rockchip_display_fixup() into board_fdt_fixup();
Change-Id: Ib3f4e991ffd7420a8f39390ae067340a65183a26
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Most of rockchip board do not have a fastboot key, remove it
from common board init.
Boards need to add it back in per-board init if needed.
Change-Id: I8e3ae1f767485ae075811f406c6822f333d1bd78
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The serialno is used to identify the device.
Serialno can be got from vendor storage, efuse,
and generated ramdom. The order is:
vendor storage > cpuid(efuse) > ramdom
Change-Id: Ic805848d59eec761fe1eac6ee43558b2ba06e3c8
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Using fdt_translate_address() instead of fdtdec_get_addr() to avoid
address parse error when 64-bits CPU works at 32-bits mode but uses
64-bits DT files.
Change-Id: I8c605ab2e5b3fc0d5267af6094c2a7f54c2d7e89
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
pmucru isn't referenced on some platforms, so pmucru driver can't
probe that the "assigned-clocks" is unused.
Change-Id: I390b302c9101f87dcd9264fda39e1f2e0e66d2b3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
1. support adc value recognize;
2. support gpio value recognize;
Change-Id: I8bcbdd914405184d46029c4995c09b09e36c7ea3
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Rockchip may use miniloader instead of SPL, in this case, the iomux
for uart intput is setting, we need to init it in boart_init().
Change-Id: I1ad4fc8cef1aeb222c284dfaf5c2d34a3f1625dd
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Load dtb from mmc/nand, rebuild live dt and scan dev.
Change-Id: If079b23702d0df333b62a14fcf3f6c2c37d3d670
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We use common board/spl/tpl file for all rockchip SoCs,
- all the SoC spec setting should move into SoC file like rk3288.c;
- tpl is option and only purpose to init DRAM, clock, uart(option);
- spl do secure relate one time init, boot device select, boot into
U-Boot or trust or OS in falcon mode;
- board do boot mode detect, enable regulator, usb init and so on.
Change-Id: I7b5fa1e3e6e5f4a30a382003215425530087a586
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
lowlevel_init() is never needed for rk3288, so drop it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
The current code picks the first available clock. In U-Boot proper this is
the oscillator device, not the SoC clock device. As a result the HDMI display
does not work.
Fix this by calling rockchip_get_clk() instead.
Fixes: 135aa950 (clk: convert API to match reset/mailbox style)
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Enable fastboot feature on rk3288.
This path doesn't support the fastboot flash function command entirely.
We will hit "cannot find partition" assertion without specified
partition environment. Define gpt partition layout in specified board
such as firefly-rk3288, then enjoy it!
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
If we would like to boot from SD card, we have to implement mmc driver
in SPL stage, and get a slightly large SPL binary. Rockchip SoC's
bootrom code has the ability to load spl and u-boot, then boot.
If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to
bootrom in board_init_f(), then bootrom loads u-boot binary.
Loading sequence after rework:
bootrom ==> spl ==> bootrom ==> u-boot
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip:
Signed-off-by: Simon Glass <sjg@chromium.org>
The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
provider now implements a single set of clocks. This provides a simpler
conceptual interface to clients, and better aligns with device tree
clock bindings.
* Clocks are now identified with a single "struct clk", rather than
requiring clients to store the clock provider device and clock identity
values separately. For simple clock consumers, this isolates clients
from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
clk-uclass.h contains the provider API. This aligns with the recently
added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
can customize these operations if needed. This also aligns with the
recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.
Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.
test/py passes for sandbox (which invokes the dm clk test amongst
others).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
At present the low-level init is skipped on rockchip. Among other things
this means that the instruction cache is left disabled. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288
Add code for starting up U-Boot SPL and U-Boot proper. This is generic and
makes use of devices provided by the board- or SoC-specific code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Joseph Chen
Jason Zhu
YouMin Chen
Kever Yang
William Wu
Finley Xiao
Frank Wang
Jacob Chen
Xu Ziyuan
Simon Glass
Stephen Warren
huang lin