Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as
stand-alone devices. Useful in particular for systems that support
DM_ETH and have a stand-alone MDIO hardware block shared by multiple
Ethernet interfaces.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I8e106f4360aa46289e0ed551f8f685cad9dc6269
No commands are necessary to have a network stack.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Duncan Hare <dh@synoia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I84cbc5d7fc65f2f4b9b85285226727d3f43363ab
The DMA may attempt to write a DMA descriptor in the ring while it is
being updated. By writing the DMA descriptor buffer address to 0, it
is assured the DMA will not use such a buffer and the buffer can be
updated without any interference.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: If70a57f195c146d571de20385b55ff75f7dea7db
This patch prevents an issue where the RX packet might have been
accessed by the CPU, which now has cached data from the packet in
the caches and possibly various write buffers, and these data may
be evicted from the caches into the DRAM while the buffer is also
written by the DMA.
By invalidating the buffer after the CPU accessed it and before the
DMA populates the buffer, it is assured that the buffer will not be
corrupted.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6271396aad6abac3fb11e5e742a3b2c9e7cc355b
The current code polls the RX desciptor ring for new packets by reading
the RX descriptor status. This works by accident, as the RX descriptors
are often in non-cacheable memory. However, the driver does support use
of RX descriptors in cacheable memory.
This patch adds a missing RX descriptor invalidation, which assures the
CPU will read a fresh copy of the RX descriptor instead of a cached one.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia05e8a43d707088bc3699b7d00434c8d12d2692f
Currently the code only flushes the first RX descriptor, not every entry
in the RX descriptor ring. Fix this, to make sure the DMA engine can pick
the RX descriptors correctly.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7a37f8a1fd51b2b7ca4fb557885d711ebd72c49c
This code programs the next descriptor in the TX descriptor ring into
the hardware as the last valid TX descriptor. The problem is that if
the currenty descriptor is the last one in the array, the code will
not wrap around correctly and use TX descriptor 0 again, but instead
will use TX descriptor at address right past the TX descriptor ring,
which is the first descriptor in the RX ring.
Fix this by adding the necessary wrap-around.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iaf0f5dba76c232af1cbef628c099aaf43542757d
The RX descriptor field 3 should contain only OWN and BUF1V bits before
being used for receiving data by the DMA engine. However, right now, if
the descriptor was already used for receiving data and is being cleared,
the field 3 is only modified and the aforementioned two bits are ORRed
into the field. This could lead to a residual dirty bits being left in
the field 3 from previous transfer, and it generally does. Fully set the
field 3 instead to clear those residual dirty bits.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I5b116fa58de65b3958c3ddd87f6c182c532b9542
Add management of property "reg" to configure @ of phy and
also "max-speed" property to specify maximum speed in Mbit/s
supported by the device
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6ecabcffc4782f1e641d8ee1021f6c3caf360707
Add management of property "reset-gpios" in the node identified by
"phy-handle" to configure any GPIO used to reset the PHY.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia7dfcafc2e2f90a5ca48205dd2562fb62a3d6d84
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to
phy_connect(). Passing 0 used to work before be accident, but does no
longer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibc8a780b8a7e1be6f827ca901d0b1f2b384ca627
Align the board and driver prototype for board_interface_eth_init
to avoid execution issue (the interface_type parameter is defined
as int or phy_interface_t).
To have a generic weak function (it should be reused by other driver)
I change the prototype to use directly udevice.
This prototype is added in netdev.h to allow compilation check
and avoid warning when compiling with W=1 on file
board/st/stm32mp1/stm32mp1.c
warning: no previous prototype for 'board_interface_eth_init'\
[-Wmissing-prototypes]
int board_interface_eth_init(int interface_type, ....
^~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7301e49ef8e51ecdde0629a69d7bcc07465952d0
This patch solves many warnings when compiling with W=1:
warning: no previous prototype for '....' [-Wmissing-prototypes]
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ice01d9d56324b450f313a4a74e5039581e20a08e
Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII
with PHY Realtek RTL8211 (RGMII)
We also support some other PHY config on stm32mp157c
PHY_MODE (MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz and 50Mhz), No 125Mhz from PHY config
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ie696f22dd260f6712c61744c60dc9d5a64737a5a
Added a comment on the limitations of phy_find_by_mask API when scanning
MDIO buses with multiple PHYs present. Added short descriptions to the
other APIs in phy.h for consistency.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ic726c545a9e2c7a68eb565e01848f6e6e9475111
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by several means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. Direct access for C45 PHYs and C22 PHYs when accessing the reachable
DEVADs.
3. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I53a73274b6386f8a510b590a0f7ce1923f7b5528
The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iae1c8e2414b655639c42f7098a097c6a0a1e5792
Now the UCLASS_ETH device "node" field is owerwritten by some network drivers in
case of Ethernet PHYs which are linked to UCLASS_ETH device using
"phy-handle" DT property and when Ethernet PHY driver needs to read some
additional information from DT. In such cases following happens (in
general):
- network drivers
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
<-- phydev is connected to dev which is UCLASS_ETH device
if (priv->phy_of_handle > 0)
dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
<-- phydev->dev->node is overwritten by phy-handle DT node
- PHY driver in .config() callback
int node = dev_of_offset(dev);
<-- PHY driver uses overwritten dev->node
const void *fdt = gd->fdt_blob;
if (fdtdec_get_bool(fdt, node, "property"))
...
As result, UCLASS_ETH device can't be used any more for DT accessing.
This patch adds additional ofnode node field to struct phy_device which can
be set explicitly by network drivers and used by PHY drivers, so
overwriting can be avoided. Also add helper function phy_get_ofnode()
which will check and return phy_device->node or dev_ofnode(phydev->dev) for
backward compatibility with existing drivers.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I31fcf01cfb19894bc90d198d9138c1fd3e25802e
Because some phy wants to export some functions [1], export.h was
including the whole phy subsystem which pulls in lots of stuff that
causes some ordering and redefinition issues. Split out the only part
that is actually needed in export.h and include it there and in phy.h.
[1] commit 9527931507 ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I201c0c637ffd3fbba5b276ac06882d399e817511
This syncs U-Boot's include/linux/mii.h with Linux kernel v4.17
include/uapi/linux/mii.h.
While we are here, this also fixes some style issues.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I9e2089fc5a8d87e09b6d1470c08ddb039171b4c2
Add clk_valid() to check for optional clocks are valid.
Call clk_valid() in test/dm/clk.c and add relevant test routine to
sandbox clk tests.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I78b1edea1f8ef54d3aa3f7610d39d79dd994d1bf
Since kernel dtb feature is enabled, U-Boot prop use the same device tree as SPL.
At sometimes there is different require for list of device tree properties to drop
for U-Boot prop, so providing this configure which has higher priority, that if it
is defined empty string, fallback to use OF_SPL_REMOVE_PROPS.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I83b97226c01c320d3a51a6cb0b181016dc5c0067
According to commit:
(40d08d0 tools: mkimage: support pack empty file for multi image)
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie370e9137b7441bd75582c95b3f60d76d8945629
As dmac aclk comes from hclk pdbus, dmac pclk comes frome pclk pdbus,
dmac aclk should be an integer multiple of dmac pclk and the same
parent with dmac pclk. so let hclk pdbus and pclk pdbus only come from
gpll.
Change-Id: Idd2f362fcf160352dcb4577ad8a13b4dbec7c65f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Since v2.80a, dwmmc controller introduced the card write threshold for
HS200 & HS400 mode. So CardThrCtl can be supported during write operation, not
only read operation.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I7f345660107c2978d2f874d36f2dffd2acdfbcb6
Fixes warning from rv1126-usbplug_defconfig:
......
warning: (ROCKCHIP_RV1126) selects ROCKCHIP_GPIO_V2 which has unmet direct dependencies (ROCKCHIP_GPIO)
warning: (ROCKCHIP_RV1126) selects ROCKCHIP_GPIO_V2 which has unmet direct dependencies (ROCKCHIP_GPIO)
......
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I2c7d64e9cdd03f3e8dcbbb948d747a67d7dff4da
Enable otp verified-boot flag verify for U-Boot proper.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I64547de92cde34f71e14b418c4c2e64ae70fa676
The v2 gpio controller add write enable bit for some register,
such as data register, data direction register and so on.
This patch support v2 gpio controller by redefine the read and
write operation functions.
Change-Id: I2adbcca06a37c48e6f494b89833cd034ba0dae29
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Do 'gpio status -a' will cause system crash, due to the pins number
error for gpio4 (last gpio controller).
Test on RV1126 IOTEST board, which has only 8 pins for GPIO4.
Change-Id: I4150abd0ca97bc4f3043eb7fcae2287818125031
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Don't verify otp verified-boot flag for every image, the same as
signature verify.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I48c230db4429c9530066d0f42de1eea7609ba4b5
For all 32-bit platforms with CONFIG_OPTEE_V2 enabled.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I991af1639a51938a880f839b2cba472495e0afc3
from kernel-4.19:
(3bd4dd9 ARM: dts: rv1126: Add CPU idle states node.)
otp and secure-otp nodes are only defined in U-Boot.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I2fcdf677bd86a477dc087d3e4986ee6cd2dfe4de
This reverts commit ef473e3642.
We merged this commit while we didn't notice that this driver gets
init voltage from legacy "rockchip,pwm_voltage = <...>", but regulator
uclass gets it from "regulator-init-microvolt = <...>". so we have to
revert this commit to compatible the legacy one.
Change-Id: I52606d9a9268659d3d77f7d29d1eed1d80b30b1e
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Alex Marginean
Joe Hershberger
Marek Vasut
Patrick Delaunay
Christophe Roullier
Alex Marginean
Carlo Caione
Pankaj Bansal
Priyanka Jain
Grygorii Strashko
Bin Meng
Fabrice Gasnier
Joseph Chen
Finley Xiao
Jason Zhu
Jianqun Xu
Hisping Lin