Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.
So add TPL stage so-that adding new features to SPL is possible.
- TPL: DRAM init, clocks
- SPL: MMC, falcon, etc
Change-Id: I8e570e6a552b37dbe7e3c9cc879f70ff64f2354e
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(update tpl text base, add memcpy/memset back)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 532cb7f5ada0cc3779c33606d760ec99f6aa847a)
configure_l2ctlr will be shared between SPL and TPL so
move them into asm/arch/sys_proto.h
Change-Id: I0702c88b1569abb1b65c29923cedbbccaa28a33a
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit a982d5156db0587f5118a118c7e9f18d4c70891d)
L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.
Cc: Tom Warren <twarren@nvidia.com>
Change-Id: I1321528829cb523dbb2500f64e4b18d70f7ec5bc
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Backed out the change to arch/arm/mach-tegra/cache.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit d9a7dcf5b8da5460a08305cdc9452f4e62dd34e5)
Instead of directly calling into the back-to-bootrom code, the RK3399
common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a
transfer back into the bootrom.
With this factored out, the spl_board_init function can not be
customised for each RK3399 board.
Change-Id: I80166207e01646445bbafe4f27cf47008f010cf4
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit cbe18f10e6943db628e779da03dad97a93c627f3)
The RK3368 TPL stage always returns to the BootROM, so it has no need
for the eMMC, SD and SPI nodes. This marks those nodes (that should
be included in SPL, but not TPL) as 'u-boot,dm-spl'.
Change-Id: I0c3d65554f01de403dd48e446991d2a545cd74fb
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 75ff0578515665a1b712275deb73be29e5ad8773)
On the RK3399-Q7, we need to turn on the on-module USB hub before using the
USB host interfaces (only the OTG interface is directly connected to the edge
connector). This drops the deprecated 'rockchip,vbus-gpio' property and uses
a fixed regulator to turn on the USB hub.
References: 26a8b80 "usb: host: xhci-rockchip: use fixed regulator to control vbus"
Change-Id: Idd2f6b48976e5ac25f06e40d6cc0cccc0e10c94b
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 46c89c8efa3e56ad8919b3a36663bb12582ed4d0)
This patch adds support for Vyasa RK3288 initial board
from Amarula Solutions.
Change-Id: I50cc01993c16caa97a6b0f9019a5433bd30adc80
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit d55af074e5a8dc85fc78f468d1f8bc96ae8b6855)
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL
enabled: this allows the use of syscon to retrieve the addresses of
GRF and SGRF (except for the early debug UART setup, which runs so
early that the device-model is not initialised).
This removes the hard-coded addresses and goes through syscon to
retrieve the base-addresses of GRF and SGRF. After that, we use
the structure definitions to locate the respective registers.
In addition to this, the inclusion of header files is also cleaned up:
- all headers are included at the beginning (there was a spurious
inclusion of the grf header from within a function)
- all #include statements for unused headers are removed
- the remaining #include statements are sorted (while keeping common.h
included in front)
Change-Id: I0ba923da4a178c9109a292e7196f6c4c35e1c24a
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit ba1657338b05337cea516dcfea6614c06f771613)
To support bootstage recording, we want to mark our DM timer as the
tick-timer; this triggers the support for 'trying harder' to read the
timer in the Rockchip DM timer driver, even if the device model isn't
ready yet.
Change-Id: If09ee9ad6834bd8be99bc827471363383bce7c43
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit f041176c4672f2885ff0843f5f7a27c892fcc42c)
All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.
The underlying drivers should be responsible for the cache operation.
Remove these codes completely.
Change-Id: I8f04c721432753b34e85b19616a0b42d83a633eb
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: York Sun <york.sun@nxp.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 723b43daec7ee2ddb600cfcb9b0253d4a71c3915)
This allows to scan the DT including all "clocks" node's sub-nodes
in which fixed-clock are defined.
All fixed-clock should be defined inside a clocks node which collect all
external oscillators. Until now, all clocks sub-nodes can't be binded except
if the "simple-bus" compatible string is added which is a hack.
Update test.dts by moving clk_fixed node inside clocks.
Change-Id: I9c346d812b0ee270f9b6fc6b6f60af7c28ebb46e
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit ee87a097b0f66158ce2985940a5f28ba15a3552d)
Add a convenience macro to iterate over subnodes of a node. Make use of
this where appropriate in the code.
Change-Id: Iae0fb554472d0b5819d26becbbcf8909ff891514
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 3991f42ed2e38aff28ba3c24369bfbd90620bea7)
Import include/linux/dma-direction.h from Linux 4.13-rc7 and delete
duplicated definitions of enum dma_data_direction.
Change-Id: I9c6569e4ab91ac82fb1c99a38003a1ac48061813
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit b27af39935855c88ef2203dcfc1ff54e013237c4)
Add space around operator "+", make it
match the coding style.
Change-Id: I5cb1e3cea056db89d7ac0c16c233228d39bf6675
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 347e30e1720ea6c0231f81d278b076a39280a314)
Macro VA_BITS and PTE_BLOCK_BITS are not used
in the code, so remove them.
Change-Id: I5a6b900c8d1d145f28d1604c9b614226c20159d5
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 4f84cb980fdc25d7735fe114021b4a84ea601b9f)
It helps when enter rockusb mode in setup_boot_mode()
and rockchip_dnl_mode_check().
Change-Id: Iae0a88ab5e971c8d85a59ba2bef077c7c3a9e5ed
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
For cortex-A7 core, when ACTLR.SMP is 0 during the processor
power-up and power-down procedures, the caches are disabled
regardless of the SCTLR.C bit setting. It's similar for other
cortex A series core.
Change-Id: I69512787015d651fe5bb5d6961f5ed01c2505058
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
devtype can be "emmc" or "rknand", devnum is usually 0.
Change-Id: Ie90169ab2c164e9d91f3365c3d9c99278bf9c8c4
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
There are two ways to get boot mode: misc partition and
CONFIG_ROCKCHIP_BOOT_MODE_REG, we unify them in the
rockchip_get_boot_mode() function.
Change-Id: Ia2dd452e8df8a8d736300048f131ed43ec2ec3a3
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
blk_dread returns negtive error code or blocks number
that read successfully.
Change-Id: I0f2afe98cfb64fe8e83a065fa64b91481856f5be
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Rockchip release bl31.elf file for armv8 SoCs like rk3399, rk3328,
the elf have more than one section, we need to decode it first and
packed them into u-boot.itb with its file. This script is to generate
the its script.
Need default bl31.elf in root directory of U-Boot source and dtb
as parameter.
Change-Id: Id70181b5d80beaf71458f78d274375efaf871364
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
We package U-Boot and OP-TEE into one itb file for SPL,
so that we can support OP-TEE in SPL.
Change-Id: I2c20333d6f3bb11ac1ec4bbb32c901028fb15d64
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Set ddr as non-secure so that mmc dma can access.
Change-Id: Ia0f51908a8d428b864a9d71b2a3dd8baeb79b952
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We are not ablt to go on if we do not able to get some image which
is must.
Change-Id: I1cebd327ec894c688f57627518df85f6ff4aa836
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This CRC32 driver is from: remotes/origin/rkdevelop.
RK format images is packed by mkknlimg tool, it adds the
CRC32 checksum which is not standard into image header,
so this CRC32 function is only used for rockchip platforms.
Change-Id: Ia52c6efa9dede148b1cb448691380f2d3184cd5e
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
We use blk_desc instead of interface from BLOCK_API, and move parameter
into disk/ as a standard partition format.
Change-Id: I6923ef1c23fa6ba1d614dfca079599e87c123ccc
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
- support both gpt and rkparameter
- using blk_desc for read/write instead of rkblk api
- add a rockchip_get_resource_file() API for those image alread in RAM;
- try to get resource from AOSP boot.img/recovery.img first instead of
RESOURCE partition.
Change-Id: If7eb53723821b48e26a392bb18a3114faf35748a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Rockchip use rkimg bootloader to boot Android during development cycle and for
other OS, typical content kernel.img with zImage/Image, boot.img and
recovery.img with Ramdisk, packed with 'KNRL' header; and resource.img
with dtb and uboot/kernel logo bmp, vendor storage for custom info
like SN and MAC address.
Change-Id: I400195a5e622437f234f22d6675a5e96db9085c6
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The rk3288-evb-rk1608 is a development/evaluation for RK3288
and RK1608. The RK3288 as Host AP, and the RK1608 as a
Dual-cores DSP coprocessor, it provides high-performance
professional computing capabilities to Host AP.
They communicate with each other through MIPI and SPI. There
is a good host environment on host RK3288, we can easily debug
RK1608.
Also, the rk3288-evb-rk1608 is different with rk3288-evb, so
we need to add a independent BSP configuration for rk3288-evb-rk1608.
Change-Id: I75ec0e14ee88acd9de7f809d7e88bca97a77a5c2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
As the emac need get the 50MHz frequency and the parent clock is dpll,
So we will update this to fix it.
Change-Id: I5b8f344dab263e9e0df72bf521394984b59ea9fe
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
We should return a errno when failed to get a valid image.
Change-Id: I2290539bc5c874312940cedc9325cc16146ce6ce
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
1. set read latency configure;
2. set lcdc cpu axi qos priority level;
3. set GPIO1_C1 iomux to gpio, default sdcard_detn;
4. disable interrupt of rk3126.
Change-Id: Iebd980e68f4a9fccbf8d620bac0f103571e1d4de
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
RK3126 can use most code from RK3128, but at some situations we have
to distinguish between RK3126 and RK3128, so this macro gives help.
It is usually selected in rk3126 board defconfig.
Change-Id: Ifd8588efb0441bd58129d9942aaacec8232f1f20
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
It supports rockchip platforms individual conversation
between U-Boot and ATF via ARM SMCCC.
Change-Id: I75077219f409e075bd3d0b312b2d85c205d6a96f
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
According to rk3036 TRM, should be set to '1' for the pll
integer mode, while the '0' means the frac mode.
Change-Id: Ibd35723d471e3091d8846c700aca128ac5ca0327
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
After the MASK MACRO update, we need to update the driver at the same time.
This is a fix to:
37943aa rockchip: rk3036: clean mask definition for cru reg
Change-Id: I23504454f5df17cff332ca5096928f1079e83bf6
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.
Change-Id: I53141ddf7679bd6e2f414b2ce0171f8e0df65297
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
MMC and RKNAND are under blk framework, so they
can be accessed via blk_dread/dwrite, and the SPI
Nor Flash is under spi framework, which need to
accessed by spi_flash_read/write.
Change-Id: Ieaefc571846d29d5ca779c501661378e456fed95
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Use "rockchip,rk3128-usb" for the compatible to both work with
U-Boot and kernel dts.
Change-Id: Ib6016c3961cbc2793ad49ec1be9466b1da914950
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
TODO:
Switch back to SoM defined GPIO3_C4 when SoM HW ready.
Change-Id: I58c4fc0b6ec330d3b5ebe62c974605c3a5111c8b
Signed-off-by: Cody Xie <cody.xie@rock-chips.com>
Don't set env "preboot", set reboot flag instead.
And let setup_boot_mode to do the mode change.
Change-Id: I3de480fc306255f31a7ae99e2186e6345df36ca8
Signed-off-by: Cody Xie <cody.xie@rock-chips.com>
Jagan Teki
Philipp Tomsich
Bin Meng
Patrice Chotard
Simon Glass
Masahiro Yamada
Andy Yan
Joseph Chen
Kever Yang
Jason Zhu
Xing Zheng
Caesar Wang
Jerry Xu
Cody Xie