Let the CPU stop working earlier so that the last operation
of spinand can be maintained at a better power supply level.
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I5bb008abaa6d5da3431f2edcee50579f7ab14eff
add not_save_power_en to judge whether save the PMIC_POWER_EN register.
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I6e2117ca947dacee41eead631a5c877bd6be3e7a
Allow modules to be omitted from CONFIG_SPL_POWER_SUPPORT.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Iaa3291d8bfc99c24ac01897fccb9ea7d6677927d
Add DFU to read and write to MTD base storage.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I84cb160b182c31d7f84ed700896a4970845a3ca8
rng module is not belongs to crypto driver anymore.
Change-Id: I6d837397621267edb586034ff87b82fc33a30d5b
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Add a driver for the rng device found on rockchip platforms.
Support rng module of crypto v1 and crypto v2.
Change-Id: I5be779aa08452977965d032e366f4e36c930b12e
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
(cherry picked from commit b072d00c225e5b8147ed7444ebeae4ddd336870b)
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Add a uclass for reading a random number seed from a random number
generator device.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit a2487684003b0bc380955e1a38cdd71da3ca4366)
Change-Id: Ife2287132db695181d663653f2ceaab0e343b41f
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
The Rockchip DWC3 controller only support DRD mode (Dual Role
Device), but not support OTG mode. So if the dr_mode in DTS is
configured to OTG, then we force it to Host mode. This patch
does not affect the device function of OTG, such as rockusb.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I806623aa9b0bb8b595417755db7d9c6b6c4f38f1
The current 4-minute data transfer timeout is misleading and broken.
Instead of such a long wait, calculate the timeout duration based on
the length of the data transfer. The current formula is the transfer
length in bits, divided by a multiplication of bus frequency in Hz,
bus width, DDR mode and converted the mSec. The value is bounded from
the bottom to 10000 mSec.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I168b6ceba917d3e621559a92a63fac78abca6bff
(cherry picked from commit 4e16f0a67d80b4ce11995b870b5d9c8d11266d0d)
The function has a little fix during upstream review, do fix to sync
with upstream.
Change-Id: I9e1c43a660b2f83395d1639aa962988ca04494e5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
1.reserve for GPT
2.kernel spinor erasesize is 64KB
Change-Id: I32a5b26f8f39b4b226ec54342ce5d8d3d71f1c4d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This adds the necessary data for handling otp on the rk3568.
Change-Id: Id5e8a3a1561604bb307ef17e06d11d7e62d8a840
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add more condition to decide which dev is "mtd 2".
More info seen in 82ee425415.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Iea84b5a7307969dad785f3136b0af8b9f45e94f6
shengfei Xu
Sandy Huang
Jon Lin
Guochun Huang
Jason Zhu
Joseph Chen
Wenping Zhang
Yifeng Zhao
Lin Jinhan
Sughosh Ganu
William Wu
Jianqun Xu
Wyon Bi
Tang Yun ping
Weixin Zhou
Finley Xiao