Add logging to aid debugging features in these drivers. Also drop some
code in sandbox_spi_xfer() which is not used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I736a761d9651dc17de0649f191ed717ea37a3fc6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c3aed5db591ee38068dc2b6d73b04638bd7b7b26)
At present we support specifying SPI flash devices to use in the device
tree and on the command line. Drop the second option, since it is a pain
to support nicely with driver model, and unnecessary.
Change-Id: Ic9e8e6cd69fb6bfa3a7cf26e51d454c4794cd18d
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 1289e96797bfd6311f3dc656fc515a882b82701b)
This patch adds support for 2 new XMC (Wuhan Xinxin Semiconductor
Manufacturing Corp) SPI NOR chips.
This support can be enabled by selecting the SPI_FLASH_XMC Kconfig
option.
Change-Id: Id0f9eec62f9c99d085e2cba550cd2e0fd77f1261
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 881e4fc206fb0e7466b532665655647b5956b65e)
Add ISSI to Kconfig to make it selectable via menuconfig.
Also convert all current platforms.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I623a8e29359455055f7d20ad60bb8972846bec6e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 13f451bf5625e222e881779e69d92a2002e41dfc)
Add support for SPANSION s25fl128l
Change-Id: I52bc8fe66c45a196bc688c1eb5a55af322ea0b52
Signed-off-by: Clément Laigle <c.laigle@catie.fr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: fixed , at the end of } ]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 04d57b1d588aeda00f308028aad6239467f24923)
This commit adds paired dev info for winbond w25q16jv
(tested w25q16jvssiq with a i.mx6 board)
Change-Id: I71adbc8b57960d6c4f1f9a0d45a1b5f92cc72f43
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 51b2411946e5f247f26fde41a7227a002270d376)
Add support for the Macronix mx25l1633e nor flash. (Tested on a imx6 board)
Change-Id: If15d3a6fcf78a95c798966b720329d697bcb1bbd
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 70cff76c38a7051992e399f35e1571f24efbfded)
Add support for the Gigadevice gd25q16c nor flash. (Tested on a imx6 board)
Change-Id: I7382793b94bbe142346dfdd601bbd3f5d77e20e6
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b1360e2fc9b45650e1744138702dc6938962d608)
This commit adds the following flashes to the id-table
- W25Q16JV
- W25Q32JV
- W25Q64JV
- W25Q128JV
- W25Q256JV
Change-Id: Ic5873a7292d9b706b2839feb84c171d8cb1f5c73
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 760b75564fdf2fe53d8c4069a6fb3320586eb662)
Update the parameters sandbox_sf_bind_emul to support livetree.
Change-Id: Iec83b813c8cddd750f7061d697304fa05556c5fb
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 008dcddf9937bd2576f98b48eb5bf0f60ad36014)
The N25Q256(A) datasheet clearly states that this device does have
a Flag Status Register and does update FSR PEC bit 7 during Program
and Erase cycles to indicate the cycle is in progress. Enable the
FSR PEC bit polling on this device to prevent data corruption.
Change-Id: I3f2a50091513a52b9bc02c44d4a37f0bd6c8e392
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 069b746ad9e66ab75973020f992e059c06cf3a7c)
Change sector size to 256KiB in table spi_flash_ids.
Change-Id: If80ace950e8ffe6a911e10d28732e60ce2298dfd
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 51dce7d2bfdecd974412634e4a0758ac55edcc00)
Move the strdup() call so that it is only done when we know we will bind
the device.
Change-Id: Ie322cba71f94d829e6c327a921ddc64cfca64e81
Reported-by: Coverity (CID: 131216)
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit fb95283931011aef78d885f2799ad9d7367f4e48)
This flash IC is used in some chromebook models
manufactured by Bitland.
Change-Id: I40d9868d2a30ad8e28f8a06abb50130211fcf0c6
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b1f2b72e39465f2d4582bb4d8c426489ee94e2d9)
The clean_bar() function resets the SPI NOR BAR register to 0, but
does not set the flash->curr_bar to 0 , therefore those two can get
out of sync, which could ultimatelly result in corrupted flash content.
The simplest test case is this:
=> mw 0x10000000 0x1234abcd 0x4000
=> sf probe
=> sf erase 0x1000000 0x10000
=> sf write 0x10000000 0x1000000 0x10000
=> sf probe ; sf read 0x12000000 0 0x10000 ; md 0x12000000
That is, erase a sector above the 16 MiB boundary and write it with
random pre-configured data. What will actually happen without this
patch is the sector will be erased, but the data will be written to
BAR 0 offset 0x0 in the flash.
This is because the erase command will call write_bar()+clean_bar(),
which will leave flash->bank_curr = 1 while the hardware BAR registers
will be set to 0 through clean_bar(). The subsequent write will also
trigger write_bar()+clean_bar(), but write_bar checks if the target
bank == flash->bank_curr and if so, does NOT reconfigure the BAR in
the SPI NOR. Since flash->bank_curr is still 1 and out of sync with
the HW, the condition matches, BAR programming is skipped and write
ends up at address 0x0, thus corrupting flash content.
Change-Id: Ib8ec33a2b890ee7f1566846172c51254b0388964
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8ff4130debcc09594b550209c44abf6c7e3ee595)
Add ID for the Macronix MX25U25635F flash.
Change-Id: I0ae2cf15f262229e508af57c3a25d4a46c1286db
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a2569f12f0efaad2b1e0754a19f373275562f91e)
Add ID for the Winbond W25Q256 flash.
Change-Id: I16e11302d8006ef92d233bdfb17c0838b7e897c9
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d8c16849a90866617c6656c5d25d860be840dec9)
page size for JEDEC EXT starting 0x4d00 is 512b,
except JEDEC ID 0x215, 0x216 and 0x220
Change-Id: I0f55264c67685f7b497cffc52509277678daccde
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
[jagan: added proper commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4eaa2fa16968359ffcf207e63848ed7f3a6e4309)
Added support for is25wp032, is25wp064 and is25wp128.
Change-Id: I59a336eaf7d1491dbd802e57adf0ca366b113133
Signed-off-by: Kimmo Rautkoski <ext-kimmo.rautkoski@vaisala.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 39b9e9bc72cef52abb8532ffa92c42be9f010e2f)
Add entry for Spansion s25fl208k part.
Change-Id: Ia340455b50efeae30ef152e72d9a7083a22f468a
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4d95ed39a19565a784419c8d9d67ad1b46ce3103)
This commit adds support for the SST sst26wf016, sst26wf032
and sst26wf064 flash IC.
Change-Id: I6ceec6acfd99a0e5e0ae97f59a9a62b2a9dd1f69
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a19e97157c3721ef9c4b15c68c1773467a3b4a98)
sst26wf flash series block protection implementation differs
from other SST series, so add specific implementation
flash_lock/flash_unlock/flash_is_locked functions for sst26wf
flash ICs.
Change-Id: Id4228dde75de212d7b29dc2a621f64805fed5b48
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 3d4fed87a5fa3ffedf64ff2811cd95c5ac4503ac)
Make sure the user is notified instead of silently returning an error.
Change-Id: I727948d67e404a09a2b444296a3cd8189a3662ed
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit aa1ced7f09798700f3d96f39f6f5dc7d3d34cf66)
This SUNXI variant SPL SPI code doesn't use either SPI or
SPL_FLASG subsystems due to size constraints and also placing
this code in drivers/mtd/spi will unnecessary build SPI_FLASH
code(if defined) which never required, hence moved to arch area.
And also renamed the file according to kconfig which resembles
proper name.
Change-Id: I0bf18e93d26bc1b80d3dfa7219a2a904ed17085a
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c2a7a7ef866f2980213fee2a4a0df60fb06db6d0)
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.
This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives:
#include <libfdt.h> -> #include <linux/libfdt.h>
#include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Change-Id: I68fd5734d6460c169fa5ee2893c57cb5d73340b6
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b08c8c4870831c9315dcae237772238e80035bd5)
Add entry for ISSI IS25LP256 part.
Change-Id: I80fbd5458f5d85b8a996dec746bf196276b9952e
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 0a84925974f26023df743d2b601ab1328a485e35)
spi_flash_probe_tail is now only called from spi_flash_probe, hence we
can merge its body into spi_flash_probe.
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: Ic6703eeea65a8093339edabd02e1557711671b2b
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 36890ff0d00f6c44631a6453b355f8af1b5ddd53)
Fix two indention-related style violations.
Change-Id: I0cc90e1b0c387fcf9dc3b84c3e2caaa2bf0f417f
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a3e32c5038aa674535ba1e48e994e9368ad47055)
Commit ba45756 ("dm: x86: spi: Convert ICH SPI driver to driver model")
removed the last usage of the spi_flash_probe_fdt function, rendering it
obsolete.
This patch removes the function.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: If44d06efea34ab54b4618c0d5ec45a1859ea5245
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 74ea6e82f8f626c8c3098dea72f008e8ec0357f9)
Command bytes are part of the written bytes and they should be taken into
account when sending a spi transfer.
Change-Id: I8b38a1c15cbfc5bc5394ca59e386ddff413210fc
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6c94bd12c4adca45033ef89daafa66fbfc9acd17)
For some SPI controllers it's not possible to keep the CS active between
transfers and they are limited to a known number of bytes.
This splits spi_flash reads into different iterations in order to respect
the SPI controller limits.
Change-Id: I9e5621b1939829ff8f9ed7d4dca50bb87d27b2ef
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8af74edc30bb60a90a5c4d2769ff3129b187796e)
This spi-nor is 4Mbit/512KB
Fixes: b4fbcbc5a5 ("mtd/spi: add support for is25lq040b")
Change-Id: I0f7204f031a01c3954c1e2186e1b658c35048239
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 065592b40b41b11ee66d8ff71a55156bf1b35088)
Change-Id: I7714af2a6f097459e4d92b0abd7701629a7f918a
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b4fbcbc5a5e406731cccf62102e383f9dac62398)
The Allwinner SPI flash SPL boot support is guarded by the SPL_SPI_SUNXI
symbol. But despite its generic name, the actual only use case for this
is to provide SPI flash support to the SPL, which requires
CONFIG_SPL_SPI_FLASH_SUPPORT to be defined.
Select this symbol from the SPL_SPI_SUNXI Kconfig definition. This
avoids doing this explicitly in the defconfig, and fixes SPI booting on
the Pine64 SoPine (and -LTS version) and the OrangePi Win board (both with
SPI flash).
Change-Id: Ia1f73a4a0bcdd27a987609289f5b475ddbe92e8e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a722359de4e1f68ad2392b2eb88cfca55f129637)
The content of Bank Address Register (BAR) is volatile. It is cleared
after power cycle or reset command (RESET F0h).
Some memories (like e.g. s25fl256s) use it to access memory larger than
0x1000000 (16 MiB).
The problem shows up when one:
1. Reads/writes/erases memory > 16 MiB
2. Calls "reset" u-boot command (which is not causing BAR to be cleared)
In the above scenario, the SoC ROM sends 0x000000 address to read SPL.
Unfortunately, the BA24 bit is still set and hence it receives content
from 0x1000000 (16 MiB) memory address.
As a result the SoC aborts and we hang. Only power cycle can take the
SoC out of this state.
How to reproduce/test:
sf probe; sf erase 0x1200000 0x800000; reset
sf probe; sf erase 0x1200000 0x800000; sf write 0x11000000 0x1200000 0x800000; reset
sf probe; sf read 0x11000000 0x1200000 0x800000; reset
Change-Id: I9483ea18defb28635f951ff6a4c788f54859ac37
Signed-off-by: Lukasz Majewski <lukma@denx.de>
[Fixed comment text on clean_bar function]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ca1ac16da097bf0ab176b1a201653553160dc042)
The sunxi-specific SPI load routine only knows how to load a legacy
U-Boot image.
Teach it how to handle FIT images as well, simply by providing the
existing SPL FIT loader with the right loader routine to access the SPI
NOR flash.
Change-Id: I5191e247142685b19f2aab194baef4a1d20bd220
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Peter Kosa <kope@madnet.sk>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ba09440131a707c4fabf2875b14521bcf2b86938)
Spansion S25FS256S and S25FL256S flashes have equal JEDEC ID and ext ID.
As far as S25FL256S occures in spi_flash_ids before S25FS256S, U-Boot
incorrectly detects FS flash as FL. Thus its better to compare with
S25FS256S first.
Change-Id: Iaf2ba1c7e89d9452fb6134dbfe336dc18473273c
Signed-off-by: Vsevolod Gribov <vgribov@larch-networks.com>
[Added S-o-b]
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit db10809c17c7cd8960d0c45248bbef6e76251ad7)
The flash chip is 2 MiB , organized as 32 x 64 kiB sectors .
Rectify the entry to match the datasheet, reality and Linux SNOR IDs.
Change-Id: Ibaa80d3b07c122965b27bceb6171ba9f201a8e8e
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 545a43822226d151701f3bf9b668298a124fefc0)
Add MT35XU512ABA1G12 parameters to NOR flash parameters array.
The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
dual and quad. Supports subsector erase with 4KB granularity, have support
of FSR(flag status register) and flash size is 64MB.
Change-Id: Ia753825a18b14215b35a557a55e891cad757e6ce
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 811b6be166ee4d9eaba73ff1ae5b648d4c98b30e)
To support MACRONIX MX25U1635E 16M-BIT flash.
Change-Id: I80437215d617841a9c21cd7208ac415421eba0a6
Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6d3cb0fdcd7d29ef54651576c3d0c5fb8c789a16)
Add support for GD25Q256, a 32MiB SPI Nor
flash from Gigadevice.
Change-Id: Id28c00189058971580406270e708a126c94c0461
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
On some flash (like Macronix), QE (quad enable) bit is in the same
status register as BP# bits, and we need preserve its original value
during a reboot cycle as this is required by some platforms (like
Intel ICH SPI controller working under descriptor mode).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[Refined code for readability]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add the print message to tell us why the erase operation doesn't work.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This adds support for Macronix flash MX25U6435F (device ID 0xc22537).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Move the only use of CONFIG_SF_DUAL_FLASH to defconfig. This makes the
associated topic_miamiplus.h header obsolete, so remove that as well.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores.
To allow sharing the clocks, GPIO and driver code easily, create an
architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol.
Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and
let it be selected by a new shared Kconfig option.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Addresses passed on to readl and writel are expected to be of the same
size as a pointer. Change the parameter types of sunxi_spi0_read_data()
to make the compiler happy and allow a warning-free aarch64 compile.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Simon Glass
Stefan Roese
Michal Simek
Clément Laigle
Ludwig Zenz
Hannes Schmelzer
Marek Vasut
Ashish Kumar
Carlo Caione
Kimmo Rautkoski
Sean Nyekjaer
Eugeniy Paltsev
Liam Beguin
Jagan Teki
Masahiro Yamada
Mario Six
Álvaro Fernández Rojas
Andre Przywara
Lukasz Majewski
Vsevolod Gribov
Yogesh Gaur
rick
Andy Yan
Bin Meng
Wenyou.Yang@microchip.com
Mike Looijmans
Tom Rini