Commit Graph

9 Commits

Author SHA1 Message Date
Joseph Chen 269512fdf6 irq: clean up code
- using IRQ_X() to print message;
- update some comment;
- rename some function;
- add more strict irq sanity;

Change-Id: If5432818d4bc12fc1aa0b8aca6898bbf79dfa9fb
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2019-02-25 14:29:34 +08:00
Joseph Chen 8696cc3875 irq: add irq busy validation
return -EBUSY when this irq is occupied.

Change-Id: I75ad6c0b13e167762cab2b8f9a2b786e588b2ade
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2019-02-25 09:59:46 +08:00
Joseph Chen c15709b516 irq: init IRQ_STACK_START_IN
IRQ_STACK_START_IN is default 0x0badc0de which is a invalid address,
this patch makes all exceptions routine work normally.

Change-Id: I3f4d75b90d840f7ea1cb7a2e1cbc7ad452aef15b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2019-02-01 11:53:47 +08:00
Joseph Chen c563adc74e rockchip: add interrupt debugger to dump pt_regs
We install a timer interrupt and dump pt_regs when
the timeout event trigger. This help us to know cpu
state when system hang.

Change-Id: I91aa2322036ae83ac8b9cd299bef9b521995d85b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2018-06-13 10:56:38 +08:00
Joseph Chen c234b81e6a irq; support irq revert trigger type and get gpio level
Change-Id: Ib897bb37c518429c595903bb8f2cfd9fcea9aa78
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2018-01-30 17:25:14 +08:00
Joseph Chen ed837edf98 irq: support irq suspend and resume
U-Boot will support cpu suspend/resume, cpu and logic may
lose power, this patch guarantees gic works normally.

Change-Id: I8ebee881fa27fea075502f962f9faabaa8264f67
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2017-12-05 09:34:48 +08:00
Joseph Chen 0e508c4fef drivers: irq: disable irq before free irq handler
It makes irq handler free safely

Change-Id: Id3af8956d5681881301e658a1adb9ca3aba97f79
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2017-10-23 09:27:58 +08:00
Joseph Chen 42865eb5ad drivers: irq: deliver both irq and private data to irq handler
gic irq handler only need private data, while gpio irq(parent bank)
handler needs private data and irq number for getting gpio bank and
pin information. So we need deliver both of them to the irq handler.

This patch fixes the legacy code issue.

Change-Id: I1917b588a867e807cbd15e2e4101ae259cf4a40f
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2017-10-12 09:41:08 +08:00
Joseph Chen 4e6670fe63 drivers: add irq interrupt framework support
This patch add support for IRQ interrupt, FIQ not included.
It will be enabled when you select CONFIG_GICV2 or CONFIG_GICV3.

The framework support gic interrupt and gpio interrupt, relative APIs
are provided in: ./include/irq-platform.h

If you'd like to add a new platform support into interrupt framework,
please follow the steps:
1. add relative definitions in the file like other platforms:
   	./include/irq-platform.h

2. add GICD, GICC and GICR(for GICV3) base address definitions in the
   rkxxx-common.h, they are needed in: arch/arm/cpu/armv8/start.S;

3. enable CONFIG_GICV2 or CONFIG_GICV3.

Notice:
1. the framework is initialize in function 'interrupt_init()' of
   _sequence_r[]. So you should not request irqs too early.

2. IRQ stack size is configured by CONFIG_IRQ_STACK_SIZE, the default
   value is 8KB when CONFIG_IRQ_STACK_SIZE is absent.

Change-Id: I3d9e29873c9d64cd28aabd13a61111438c5902b0
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2017-09-27 10:34:17 +08:00