Add cpll freq setting in rkclk_init.
If have vop display, the cpll is just for dclk vop.
The cpll freq will be setting by dclk freq set.
But if no vop display, the cpll need to set init freq for other
children clk.
Change-Id: Ia45892dd3c8efb77cf32b631329d927aceb8dd86
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
add mmc set and get phase for rk3128\rk3328\rk3368
Change-Id: Ic8d7764391165f28c54721c4af218f8623b2f3a7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
On FPGA, PLL is fake and can't give a lock state which causes
dead waiting, so that adding a debug message to easily notice
this situation.
Change-Id: Ic7dccedb3d7e5c7588da85bb4c4552b924f60e43
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Set aclk_perilp0 to 300M,
To improve the performance of dual USB transmission.
Change-Id: I3842742e87ed1d483215ec7bccb75b1c0ed503bf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We can not meet the assert condition after we update the code,
fix it so that we can enable the DEBUG option.
Change-Id: I4b3e6b30aae4480ed208f30610493a7d297e90ee
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
As clk_set_defaults() is removed in device core, so add it in clock
driver.
Change-Id: If09a9ddca27a3d1fc0747d8cafbeaacd8ef97d36
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add support to initialize gpll, bus and peri clock rate.
Change-Id: I84f496094606ac2231ea27ad9072b079c45f9f94
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Make clock ids consistent with kernel.
Support more clks to set and get rate.
Add clk dump.
Change-Id: I348c98ce81ce76af9c492a30480fcb495da7ed79
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
As clk_set_defaults() is removed in device core, so add it in clock
driver.
Change-Id: Ib5b9a7f81c738c65f2cb3e0ca74a410cda2ca1e2
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The new print format can reduce startup time.
Change-Id: I7ea53e07b8245fe4b5ef1fa15dd1f6efb176db47
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
If the gpll and npll freq is no change,don't set pll once again.
Change-Id: Ib16a0a1ff56560997b6ed4b487fc2d56928c14ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Make clock ids consistent with kernel.
support more clks to set and get rate.
add clk init.
Change-Id: I1e6b5734887e0bd5d845f1286f10eb0e3e42bc08
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
npll is for dclk, add PLL_LIMIT_FREQ for better jitter.
Change-Id: I6ac09e9bdbd1bef0eddb37835100be782b772d54
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
In kernel dtb, the rk3399 usb Host0/1 use SCLK_USBPHY0/1_480M_SRC
in addition to HCLK_HOST0/1 and HCLK_HOST0/1_ARB. This patch adds
the phy 480MHz clks for usb Host0/1 to ensure the generic ehci-driver
(ehci-generic.c) to enable the clocks successfully.
Change-Id: I0790e949bca0d7bdc4179f3232b29aa58436593f
Signed-off-by: William Wu <william.wu@rock-chips.com>
The nandc clk no need div 2.
Change-Id: I9e33ef3a4b5c5dcd024f3aed26ddee9fb8e6af6c
Signed-off-by: Yifeng Zhao <zyf@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The initial voltage may be too low for 816MHz and it is enough for
600MHz.
Change-Id: Ifa1438d8d3056c9fb8fb3e578a28c26682a27e46
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
As clk_set_defaults() is called before rk3308_clk_probe() and pll rate are
assigned when clk probe at present, so if enable kernel dtb and it contains
"assigned-clocks" property, the pll rate will be zero when set and get clk rate.
In order to fix this, check and assign pll rate before set and get rate.
Change-Id: Ic8e9fcf487e7531a8ef23f54d0786e0cbc9a9f4a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Some divisor calculations were misrounded, causing higher than
requested rates on some clocks. Fix them up using DIV_ROUND_UP.
Change-Id: Ie90598d94e9a8dcde9c68ec9986ea200293c2d5b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
We use ofdata_to_platdata() to get cru base from dtb,
update the api with support for live dt.
Change-Id: I652c82a427693093d4ceca5d747543af945b0986
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
support PLL freq setting,
support bus and peri clk freq setting,
support aclk vio and dclk vop freq setting.
Change-Id: I894552c1e1bb1bd13a143e200edf289234a53c1d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
pmucru isn't referenced on some platforms, so pmucru driver can't
probe that the "assigned-clocks" is unused.
Change-Id: I390b302c9101f87dcd9264fda39e1f2e0e66d2b3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
We will use the rkclk_init() for rk3399 without SPL/TPL way.
Change-Id: I73a4d694ff2cb0e18f390c293971985f41d2b03d
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
We need to init platdata from of data with ofdata_to_platdata callback.
Change-Id: I9e8e9427767f9de84c9871d9a639e7fdb5319ba4
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The pre-loader(eg. miniloader) may not init the CPLL, we need to
do the rkclk_init() to init the clocks in U-Boot, or else we may
get wrong serial baurd rate in kernel.
Change-Id: I4a226e110638aa18d10df35e8d9507f6679a5678
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
If power down and power up were not done, there was an error during
pll setting again.
Change-Id: Iaa5ef558c2bff270614f08d96a70e5c847ce927c
Signed-off-by: David Wu <david.wu@rock-chips.com>
The assigned clock-rate and clock-parent is done before probe,
so it is better to get cru's reg address at ofdata_to_platdata
before probe, otherwise there is a error to use cru's red address.
Change-Id: I7af5faa931352a4ee4a495efa9b80c95066eb5c5
Signed-off-by: David Wu <david.wu@rock-chips.com>
ciu-sample is a dummy clock, which should be the same with sclk_emmc.
Change-Id: I5350774a390555153ddaee49fb9613f25f4f249b
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
We may get into clk_probe more than one time from TPL/SPL/U-Boot,
and we only need to init bus clock one time.
Change-Id: Iab0434c66d344ff57c1edd30679c3ab3bb8f2b17
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
some board request enable cpu big core clock in uboot,
refactor rk3399_configure_cpu() function, so that the little
core and big core can reuse this function to set clock.
Change-Id: I0390d22179faf91307b22348f6f9329a58f00143
Signed-off-by: Lin Huang <hl@rock-chips.com>
Some of the asserts for valid clock divisor ranges were off by one. This
patch corrects them and writes them all in a consistent way.
Change-Id: Ia87974c8e27b7414cfe9210a916d114aa81f5ccb
Signed-off-by: Lin Huang <hl@rock-chips.com>
This patch fixes a typo in the clock initialization code that caused the
PERILP1_PCLK_HZ constant to be ignored and the clock to always run at
the same speed as its parent (PERILP1_HCLK_HZ). Since we've done all our
previous tests and validation with this bug, we should probably increase
the value of the constant (that had not actually been used) to the value
that we had been incorrectly using instead.
Change-Id: I8e1725f71ea0dbacd01929b8e8a80b91dc4f17cc
Signed-off-by: Lin Huang <hl@rock-chips.com>
some board will use other uart as console output,
so add uart0~uart4 clock get rate.
Change-Id: Iafde4819cdcf3e650fe14c7c3dd9784d953ba8a0
Signed-off-by: Lin Huang <hl@rock-chips.com>
The set_parent implementations do not make sense when OF_PLATDATA is
enabled. We guard these against OF_PLATDATA and don't populate the
set_parent-op when this is the case.
Change-Id: I37c384bf6851666550b8b3902d79b9278cff5074
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.
Change-Id: I4f75d0c1e35bbe7ff0af07d05dbb42f4732d5eb7
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The RK3288 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3288 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
implement the gmac clock set parent, but simply ignore the
others' set_rate() operation and return 0 to signal success.
Change-Id: Ic1a41634aba674001beb0e7e5ca3f7f2fa008e51
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.
Change-Id: I6405c3b2ead429084118c544bcc461e0b301d77a
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.
Change-Id: I4963f03f6aea2c7196f33dae0bca38a432c80690
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The RK3399 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3399 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
simply ignore the set_rate() operation and return 0 to signal success.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: David Wu <david.wu@rock-chips.com>
Series-changes: 2
- Fixed David's email address.
(cherry picked from commit d2f1f1abafbedd3580334f2564bfea918e49522d)
Change-Id: Ic19614e75b76d8159cf03ac4adb180ca5a8688fd
Signed-off-by: David Wu <david.wu@rock-chips.com>
Linux uses the properties 'assigned-clocks', 'assigned-clock-parents'
and 'assigned-clock-rates' to configure the clock subsystem for use
with various peripheral nodes.
This implements clk_set_defaults() and hooks it up with the general
device probibin in drivers/core/device.c: when a new device is probed,
clk_set_defaults() will be called for it and will process the
properties mentioned above.
Note that this functionality is designed to fail gracefully (i.e. if a
clock-driver does not implement set_parent(), we simply accept this
and ignore the error) as not to break existing board-support.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: David Wu <david.wu@rock-chips.com>
Series-changes: 2
- Fixed David's email address.
Series-version: 2
Cover-letter:
clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates
For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC),
the parent-clock needs to be set via the DTS. This adds the required
plumbing and implements the GMAC case for the RK3399.
END
(cherry picked from commit f4fcba5c5baaaa9d477d753f97124efdb8e45893)
Change-Id: I549891987c5a3e8546b96f1f54ad575950f92b12
Signed-off-by: David Wu <david.wu@rock-chips.com>
Elaine Zhang
Sugar Zhang
Joseph Chen
Kever Yang
Finley Xiao
chenfen
William Wu
Yifeng Zhao
Caesar Wang
David Wu
Andy Yan
Lin Huang
Philipp Tomsich