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356 Commits

Author SHA1 Message Date
Elaine Zhang 88c36f1205 clk: rockchip: rk3399: fix up the assert error 
Change-Id: I8cc4f6b775243fef1f5c8e2c711eb1b16eac79a8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-28 14:51:00 +08:00
Elaine Zhang 6b5ade5a57 clk: rockchip: rk1808: fix up the clk_set_default failed 
Change-Id: If49d6def0e16b93238311885217f30a4b7a2e7c3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-10 12:04:10 +08:00
Elaine Zhang b9f5972251 clk: rockchip: rk1808: add mac clk interface 
support mac clk set rate and set parent.

Change-Id: I3b4626fd3fcc5ffdf3c58add9c1bc002bb56429a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-10 12:04:10 +08:00
Elaine Zhang 22d359b877 clk: rockchip: px30: add mac clk interface 
support mac clk set rate and set parent.

Change-Id: Iaadcb701cf37083d90a37b24f4ffba3bef9c88cd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-10 11:24:29 +08:00
Elaine Zhang 221585fb35 clk: rockchip: rk3308: support pclk_wdt get rate 
Change-Id: I001cfef774c9657b6286467dc4ef841771841895
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang ced960d2b6 clk: rockchip: rk3288: support pclk_wdt get rate 
Change-Id: I99f384344feb68ae5b91ade901df4019790ef8db
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang 33a03efd7a clk: rockchip: rk3128: support pclk_wdt get rate 
Change-Id: Ie5dbfe5bd3fdd7868a5db64b96471a5524bde462
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang 68d8964cb4 clk: rockchip: rk1808: support pclk_wdt get rate 
Change-Id: Ib204b4c014c3b4cbd35d1f335378b0b399689303
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang 8afd7ff1e3 clk: rockchip: px30: support pclk_wdt get rate 
Change-Id: I1d58d032c6f3843df3fdee65b1ee9cd3614435b1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang a4e491228b clk: rockchip: rk3368: support pclk_wdt get rate 
Change-Id: I8253532cfa6a1d492d68b0e778f625621cad5dab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
Elaine Zhang 981ee0bd7d clk: rockchip: rk3399: support pclk_wdt get rate 
Change-Id: I8634beb815d5129534c36861c2f02e62669889e9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-04-09 17:39:21 +08:00
David Wu 200683ea3d clk: rockchip: Add mac clock support for rk3308 
Change-Id: I972e2b7977f0f94164c72ae2205ec51780eb7373
Signed-off-by: David Wu <david.wu@rock-chips.com>
 2019-04-09 11:09:22 +08:00
Elaine Zhang 5561190119 clk: rockchip: rk3288: add clk_set_default 
support aclk_vio\hclk_vio clk setting.

Change-Id: Ie826c770670598161f22208f504d8762b8597811
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-02-01 16:17:34 +08:00
Elaine Zhang 524f26463d clk: rockchip: rk3066: print arm enter and init rate 
Change-Id: Iaf4ffbb61830b7bb7cef31843f0e9b75c34d08ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-25 16:19:57 +08:00
Elaine Zhang 441bfb788a clk: rockchip: rk3188: print arm enter and init rate 
Change-Id: I604c18050e8ccbbc9aa25ecd8f4379a877239d49
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-25 16:19:57 +08:00
Jason Zhu 14262c55f8 clk: rockchip: rk3328: add case SCLK_EMMC_SAMPLE 
Change-Id: Id2769eefc1692422110152e6dbec7afeb4488c8c
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
 2019-01-25 15:45:08 +08:00
Elaine Zhang 92c6b64268 clk: rockchip: rk3128: print arm enter and init rate 
Change-Id: I0be1752522a83a2d111870e5a8ac95f92bd7f9a5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:55 +08:00
Elaine Zhang 3a1c76d931 clk: rockchip: rk3036: print arm enter and init rate 
Change-Id: Ic9212c8a0f1d50006f7121957b8bd5f34d2622d9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang ec0307ef3a clk: rockchip: rk3288: print arm enter and init rate 
Change-Id: I5a6d564a973111841df6b53a4df64a54f728e116
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang 2401c256ec clk: rockchip: rk322x: print arm enter and init rate 
Change-Id: Iab7034c8cef09908a99b5a1e396f6e015da350fb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang 093fdd9f5d clk: rockchip: rk3308: print arm enter and init rate 
Change-Id: I6df66d7b5dda643dba49ee87c2a2c0544ddbcded
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang f7913bc128 clk: rockchip: rk3328: print arm enter and init rate 
Change-Id: I80ebeee0d6d8b151061d0bbb0d1d12070dcc6f98
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang ae79bf6827 clk: rockchip: rk3368: print arm enter and init rate 
Change-Id: Ib201cf442ce7398bbe8009ce9b7de9dc1f53c587
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 21:13:26 +08:00
Elaine Zhang 044bc79de9 clk: rockchip: rk3399: print arm enter and init rate 
Change-Id: Ib5e3e0f9a3e1a5b535ec852e7c58966dc0db77cf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 11:01:59 +08:00
Elaine Zhang dfce009693 clk: rockchip: px30: print arm enter and init rate 
Change-Id: I0d2a1c6bb92397210314322fd147c4a8a6e81abd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 11:01:59 +08:00
Elaine Zhang ed6f5d94b5 clk: rockchip: rk1808: print arm enter and init rate 
Change-Id: I14f0b0c95b1367266fe9c64050a602ad58208d53
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-23 11:01:59 +08:00
Jon Lin 8094aeb8cd clk: rockchip: rv1108: add NANDC and SFC clk init 
Currently RV1108 run in 1.2G GPLL.
NANDC need 1200 / 8 div = 150MHz.
SFC need 1200 / 12 div = 100MHz.

Change-Id: Ia3f401b0cf13587209d0d68d76a9891dd3bcf990
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2019-01-22 17:06:35 +08:00
Elaine Zhang 2e8ea5b0f6 clk: rockchip: rk3288: support crypto clk setting 
Change-Id: I066ec163d959b95d0928e07716e3370715aa9898
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-21 09:11:01 +08:00
Elaine Zhang fda8d87331 clk: rockchip: px30: modify the dclk divider to even 
When DCLK use CPLL alone, the DCLK timing is critical value.
The odd-divider spacing ratio is not 50%,
it will affect the setup time of the display.
Therefore, it is suggested that we use even-divider
to make the spacing ratio is 50%.

Change-Id: I07c0fd57dd1f27984f8186f1d7c2f96df2ea10a3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-16 16:44:59 +08:00
Elaine Zhang e9dcade2a7 clk: rockchip: rk322x: add clk_set_defaults for clk init 
Change-Id: Ie2bcdf77bb7cdeb9c27b482ce70e4af35fbdc8c6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2019-01-14 11:46:32 +08:00
YouMin Chen 51c830f2d2 rockchip: clk: rk3399: support 50MHz and 400MHz for ddr clock 
Change-Id: I9d3a64ce38986f2c48e1f2614bcc274340674aa7
Signed-off-by: YouMin Chen <cym@rock-chips.com>
 2018-12-29 09:37:45 +08:00
Wyon Bi 152682ed57 clk: rockchip: px30: support setting clk_i2s_out_mclk to 12MHz 
Change-Id: I53fb5ceac0c423dd90c493d6f05069569c839f4e
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
 2018-12-26 18:45:36 +08:00
Elaine Zhang 8b75ff3444 clk: rockchip: rk3399: support clk dump 
add clk_dump.
add peri clk getting rate.
modify aplll init freq to 816M.

Change-Id: I57a9c2f708c12968909b804f957e80fb0c6d3573
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Elaine Zhang cf04b7e8f2 clk: rockchip: rk3328: support crypto clk setting 
Change-Id: I9e4d58050b087c3da6649efe4d3115da2ce6dce7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Elaine Zhang a7c5f87313 clk: rockchip: rk322x: support crypto clk setting 
Change-Id: Id92acae9424fd0b200f9b4f33982f753f6123207
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Elaine Zhang 51d1c6b1dd clk: rockchip: px30: support crypto clk setting 
Change-Id: I9971fb2b6a40640d78fb259c72aac32582f8e90d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Elaine Zhang 0cde592567 clk: rockchip: rk3308: support crypto clk setting 
Change-Id: I58967fe70fbae6630fe0404414daaee6b1498b72
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Elaine Zhang 187d951b8f clk: rockchip: rk3399: support crypto clk setting 
Change-Id: I12cbaeac250f21d4cb05d8ef3ef0e9238cb3f911
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-12-17 14:17:10 +08:00
Nickey Yang 0fd8dec7ce clk: rockchip: rk3288: adjust gpll init_cfg 
This patch adjust gpll init nr/no/nf/bw values.
keep them the same as kernel RK3066_PLL_RATE_NB(594000000, 2, 198, 4, 1)
for better clock jitter when hdmi SI test.

Change-Id: I781205d860945214f3f0957882223b8846c00773
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
 2018-12-13 17:35:26 +08:00
vicent.chi 98ebaf0e5b CRU: rv1108 add emmc clk get and set 
Change-Id: I8cbfda46d2f7e84f11dbcca844d00c87559d0aa0
Signed-off-by: vicent.chi <vicent.chi@rock-chips.com>
 2018-12-01 11:40:42 +08:00
Finley Xiao 21ab40a873 rockchip: clk: rk3308: Add flag for clk_set_defaults 
Change-Id: Ic9009b35e395cfe8c2a8f8d367b75b85294c7354
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2018-11-29 20:40:09 +08:00
Joseph Chen e04b9c6bbd clk: rockchip: rk3308: add arm clk 408M support 
Change-Id: I133576889860c7bae3f722dcd53df6a50c500c35
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2018-11-29 20:40:09 +08:00
Joseph Chen c111479f4f clk: rockchip: px30: support arm clk 408M 
Change-Id: I98cd856c99ebf2cd77d1a8ff94d2e0a40f0a4bfb
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2018-11-28 16:19:30 +08:00
Elaine Zhang dcb7870427 clk: rockchip: rk322x: fix up the vop clk setting assert error 
Change-Id: Ied72bcb5e92e300eeccd7bfd32285d2eeb4d4860
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-11-16 14:42:28 +08:00
Dingqiang Lin a2795c339d clk: rockchip: rk312x: add sfc clk init 
Change-Id: I5edf0a4b650a57a48f837fa3e007cfaf6a733f92
Signed-off-by: Dingqiang Lin <jon.lin@rock-chips.com>
 2018-11-14 14:32:24 +08:00
Kever Yang 0598134af8 rockchip: rk322x: fix clock assert value 
The value after '<' should be max value instead of 'max-1'

Change-Id: I7a1deaa75b8a931631a54e8dfd154c266251c7fc
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2018-11-08 11:03:10 +08:00
Elaine Zhang 823ecf52e2 clk: rockchip: rk3328: add clk_set_defaults for cru node 
Change-Id: I715dde89f691fd95487db53569cc6d8164dc5f28
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-11-02 09:58:36 +08:00
Kever Yang c93db2f356 rockchip: rk3229: tpl skip rkclk_init 
The new rkclk_init is too complecate and not able to run in TPL,
skip it in TPL.

Change-Id: I46f30613050a86ee74060e713283bcb7980c3348
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2018-11-01 08:40:56 +08:00
Elaine Zhang 5a616fcf52 clk: rockchip: rk3288: support aclk_vop freq setting 
Change-Id: Ifb595f244608378bff1e6443dfc017418f28ce2a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-10-30 09:09:13 +08:00
Elaine Zhang 6259b22e60 clk: rockchip: rk1808: add pll 100M config parameters 
PPLL 100M use refdiv =1 fbdiv = 150, postdiv1= 6,
postdiv2=6, vco= 3.6G, is best for pcie.

Change-Id: Ie9fddbb32baa0d4b8883b399b0e903b83afc820f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2018-10-25 14:03:47 +08:00