I just stumbled over some cluttered UBI messages. It seems some newline
chars are missing in the current U-Boot UBI source. Lets fix this
in U-Boot as well (Linux has those fixes already).
Change-Id: I21c13a3ef73aa78d4cf32721b1dd21cab186e8bd
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 78306cba118e718a3b429695ac48846b9d9afeff)
This flash IC is used in some chromebook models
manufactured by Bitland.
Change-Id: I40d9868d2a30ad8e28f8a06abb50130211fcf0c6
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b1f2b72e39465f2d4582bb4d8c426489ee94e2d9)
The clean_bar() function resets the SPI NOR BAR register to 0, but
does not set the flash->curr_bar to 0 , therefore those two can get
out of sync, which could ultimatelly result in corrupted flash content.
The simplest test case is this:
=> mw 0x10000000 0x1234abcd 0x4000
=> sf probe
=> sf erase 0x1000000 0x10000
=> sf write 0x10000000 0x1000000 0x10000
=> sf probe ; sf read 0x12000000 0 0x10000 ; md 0x12000000
That is, erase a sector above the 16 MiB boundary and write it with
random pre-configured data. What will actually happen without this
patch is the sector will be erased, but the data will be written to
BAR 0 offset 0x0 in the flash.
This is because the erase command will call write_bar()+clean_bar(),
which will leave flash->bank_curr = 1 while the hardware BAR registers
will be set to 0 through clean_bar(). The subsequent write will also
trigger write_bar()+clean_bar(), but write_bar checks if the target
bank == flash->bank_curr and if so, does NOT reconfigure the BAR in
the SPI NOR. Since flash->bank_curr is still 1 and out of sync with
the HW, the condition matches, BAR programming is skipped and write
ends up at address 0x0, thus corrupting flash content.
Change-Id: Ib8ec33a2b890ee7f1566846172c51254b0388964
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8ff4130debcc09594b550209c44abf6c7e3ee595)
ftsmc020_init is not used anymore.
So it can be removed.
Change-Id: Ieb504bd6fd84400e46fcf70b16272ed401db8360
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Add ID for the Macronix MX25U25635F flash.
Change-Id: I0ae2cf15f262229e508af57c3a25d4a46c1286db
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a2569f12f0efaad2b1e0754a19f373275562f91e)
Add ID for the Winbond W25Q256 flash.
Change-Id: I16e11302d8006ef92d233bdfb17c0838b7e897c9
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d8c16849a90866617c6656c5d25d860be840dec9)
Since 'commit f82290afc847 ("mtd: ubi: Fix worker handling")',
when booting from NAND, on a fresh NAND just after being flashed (and
only in this case), we got the following log:
ubi0: default fastmap pool size: 200
ubi0: default fastmap WL pool size: 100
ubi0: attaching mtd2
ubi0: scanning is finished
ubi0 error: ubi_update_fastmap: could not find any anchor PEB
ubi0 error: ubi_update_fastmap: could not find any anchor PEB
ubi0 error: ubi_wl_get_peb: Unable to get a free PEB from user WL pool
ubi0 error: autoresize: cannot auto-resize volume 1
UBI error: cannot attach mtd2UBI error: cannot initialize UBI, error
-28UBI init error 28
After analysis, in ubi_wl_init(), when performing schedule_erase(),
thread_enabled flag is not yet set to 1, which forbids ubi_do_worker()
to execute pending works.
This has to effect to not populate ubi->free with free physical
eraseblocks.
Following Richard Weinberger's advice, this patch has been
backported from kernel tree :
'commit 1cb8f9776c7d ("ubi: fastmap: Implement produce_free_peb()")'
Tested-by: Patrice Chotard <patrice.chotard@st.com>
Change-Id: I9ca7778757d9b578a75368a8e3fdbc990c3ed6dc
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 65c3d25a6a21b5cf4d978f05f84aaeb6b250e636)
page size for JEDEC EXT starting 0x4d00 is 512b,
except JEDEC ID 0x215, 0x216 and 0x220
Change-Id: I0f55264c67685f7b497cffc52509277678daccde
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
[jagan: added proper commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4eaa2fa16968359ffcf207e63848ed7f3a6e4309)
Added support for is25wp032, is25wp064 and is25wp128.
Change-Id: I59a336eaf7d1491dbd802e57adf0ca366b113133
Signed-off-by: Kimmo Rautkoski <ext-kimmo.rautkoski@vaisala.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 39b9e9bc72cef52abb8532ffa92c42be9f010e2f)
Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. This may vary for different parts and
hence use it from onfi parameter page value.
Change-Id: I16512bb8cb560148af32c7746d23539a6676c466
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9fdde6c4bbb6840dd175f0c29dfcc791fc0c1d2a)
This patch adds support for 16-bit buswidth by determining
the bus width based on mio configuration.
Change-Id: I821bb2d5fe8bc8e5173d590ae408f16d767a083f
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9ca8388059de8f10e035fbdcaa418ec3caeb0599)
The Tegra NAND driver recently got broken by ongoing driver model resp.
live tree migration work:
NAND: Could not decode nand-flash in device tree
Tegra NAND init failed
0 MiB
A patch for NAND uclass support was proposed about a year ago:
https://patchwork.ozlabs.org/patch/722282/
It was not merged and I do not see on-going work for this.
This commit just provides a driver model probe hook to retrieve further
configuration from the live device tree. As there is no NAND ulass as of
yet (ab)using UCLASS_MTD. Once UCLASS_NAND is supported, it would be
possible to migrate to it.
Change-Id: Idc7dc3440cc6158d61bf41150bde9c5010e30486
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4b11a6296aab84b628434cdbdd15697fab8a3a93)
As per the IFC hardware manual, Most significant byte in nand_fsr
register is the outcome of NAND READ STATUS command.
So status value need to be shifted as per the nand framework
requirement.
Change-Id: I0cb0278f83f3ea6d3768660dcb3e169e47fcbdd1
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e8c669a3e6ec9b33aea55e957024f97300b99c1c)
Number of ECC status registers i.e. (ECCSTATx) has been increased in
IFC version 2.0.0 due to increase in SRAM size. This is causing
eccstat array to over flow.
So, replace eccstat array with u32 variable to make it fail-safe and
independent of number of ECC status registers or SRAM size.
Change-Id: I00699a36b57beed284afeccf44001ee4373d9bb6
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f195fad178979020b226671cafec9f9592860174)
CONFIG_NAND_ZYNQ selects CONFIG_SYS_NAND_SELF_INIT, so the
driver doesn't have to play any ifdef game.
Also, we can mark zynq_nand_init() as static and get rid
of the mach-specific nand.h header.
This is really a revert of:
"mtd: zynq: nand: Move board_nand_init() function to board.c"
(sha1: 310995d9f91ae56082b49be06fe8c3d01424f8f6)
Change-Id: I3d435d645c911c88bdf1d25600896141cd37d54e
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 41b7d7f241221ab9f0888f47f31226cfa74a971a)
This driver is currently broken, refusing to initialize properly.
The reason is that get_nand_dev_by_index() was being called before
nand_register(), thus returning a pointer into uninitialized memory.
In other words, the struct mtd_info used by the driver is total junk.
Fix it by getting the correct struct mtd_info, via nand_to_mtd()
on the driver's struct nand_chip.
Tested on a custom board, where the CPU is halted without this patch.
Change-Id: I372eca6bfe6e6ca53612d8f2d8bcc5cdfe620222
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 07c5cbbd1e6573e169687da873db37503a1f8b60)
Add entry for Spansion s25fl208k part.
Change-Id: Ia340455b50efeae30ef152e72d9a7083a22f468a
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4d95ed39a19565a784419c8d9d67ad1b46ce3103)
This commit adds support for the SST sst26wf016, sst26wf032
and sst26wf064 flash IC.
Change-Id: I6ceec6acfd99a0e5e0ae97f59a9a62b2a9dd1f69
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a19e97157c3721ef9c4b15c68c1773467a3b4a98)
sst26wf flash series block protection implementation differs
from other SST series, so add specific implementation
flash_lock/flash_unlock/flash_is_locked functions for sst26wf
flash ICs.
Change-Id: Id4228dde75de212d7b29dc2a621f64805fed5b48
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 3d4fed87a5fa3ffedf64ff2811cd95c5ac4503ac)
Make the cfi_flash driver compatible with a live device tree.
Change-Id: Iec5b202b4ee94bbf3a129147037abe647978ab3f
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8bfeb33c463296af38432c3dbfb976f45545e381)
Add driver for the RPC block in Hyperflash mode. This driver allows
access to a CFI Hyperflash attached to the RPC block and does not
support RPC in SPI mode.
Change-Id: Ifb30047694ea0ef39f5d7f7b4181cce338a8f245
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a405a55ba8daf70311a1831938bbdc1ed92c5a83)
In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for
size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed
to 0xFFFF and the same macro is used in nand write and so that getting
nand write error.
This patch reverted this macro to the 0xFFFF0000 and used
ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function
which is equal to 0xFFFF.
Change-Id: Iae3ff9baf6bb1c05512c8432c346fafbb1bf6225
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6fbbe2d8f671920948a0b1882c6884cfdd0cbe67)
Move the NAND parameters from defconfig files to Kconfig for SUNXI
architecture only. Fort now only the CHIP pro is migrated.
It would have been better to convert this defconfig entry to Kconfig for
all supported machines/architectures but it has been abandoned due to a
fairly high amount of errors reported by the moveconfig.py tool. This is
due to defines quite often being multiplications of values/other defines
not correctly handled.
Change-Id: I9010719934b53180d2af15e45acabc45dd39d039
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 748b5b34d3d0e67923cac5f8606b7a209e063df6)
Remove NAND_SUNXI from the CHIP pro defconfig to be automatically
selected depending on the state of ARCH_SUNXI.
Change-Id: I49bec5ad57be81004a5836adeebd40b5fabe55e4
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b56052f4ca40d0d8b29fb7bd3be4c104618e4fc8)
Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the
number of entries to add in defconfig files when adding NAND support.
For now, the only board using it is the CHIP pro.
Change-Id: Ia308aa9a877a06912571510d18a00e3aaaff0403
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6d094d535c121637775b5108f1e78e426017f757)
Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I
in Kconfig.
Change-Id: I8fb0229aa90d5b837c3f2a735dc1b169dca37b06
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 663e8a9b54ccbc9b939e4e3696a84fdf2f5a43fc)
SPL support was first written to support only the earlier generations of
Allwinner SoCs, and was only really enabled on the A13 / GR8. However,
those old SoCs had a DMA engine that has been replaced since the A31 by
another DMA controller that is no longer compatible.
Since the code directly uses that DMA controller, it cannot operate
properly on the later SoCs, while the NAND controller has not changed.
There's two paths forward, the first one would have been to add support
for that DMA controller too, the second to just remove the DMA usage
entirely and rely on PIO.
The later has been chosen because CPU overload at this stage is not an
issue and it makes the driver more generic, and easier to understand.
Change-Id: I6c237da0e67d520568903d77c84103c98730ccc2
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6ddbb1e936c78cdef1e7395039fa7020c5c75326)
Move the ecc_bytes array out of nand_max_ecc_strength() for future use
by nand_read_page().
Change-Id: I0dc537a460183bc3352adfbe2163eab84d3cdbeb
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 7440bd7885da984dc20e2e8c8a0b167911e9dce1)
Prepare the future use of an helper to move the data pointer (the
column) of the NAND chip by renaming nand_reset_column() to
nand_change_column(). Resetting the column is just a matter of giving 0
as argument.
Change-Id: Ie311136768de7f7d6e92eb56afe1af9b39d4d93d
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 22f0aa0528a48cb9eb72abb065071e47c4215af9)
When changing the column, the ONFI specification states that a minimum
time of tCCS (Change Column Setup time) must elapse between the last
address cycle is asserted on the bus and the first data cycle is
clocked. An usual value for average NANDs is 500 nanoseconds. Round it
up to 1 microsecond to be safe.
Change-Id: If9f02bf0861da520e9c7e6288e41986cbb8fbe0e
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4dac80a5e991dd3b5b99910d7927edfdf4c99bb3)
Executing a command is matter of always doing the following sequence:
* Waiting for the FIFO to be empty so we can fill it with the new
command.
* Clearing the status register.
* Writing the command in the FIFO.
* Waiting for the command to finish.
Add a nand_exec_cmd() helper to handle this instead of repeating the
logic through the various functions.
Change-Id: If33cb5d361838472d12580c97a5ddaed80f08945
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a084cb6664e0de40f33da1c8ec6de816a9852f6d)
It is best practice to always clear the status register before executing
a command to be sure that the status read afterwards is relevant.
Change-Id: I70a36f514d8f820521541ed0b7473dc31f9c5824
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 781e70cff12916ae6698cc77a22e0ce687f39e3b)
One bit in the control registers indicates if the NAND controller is
ready to receive a new command. Otherwise, the command FIFO is full and
we should wait for this bit to flip. It then states that the last
command has been processed and the FIFO is now free to welcome another
command.
Add this sanity check before starting any new command.
Change-Id: I55a93fc0b3f889c40cf0e4fbb40eeeb3e46df17b
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 60fb17913354757d015ade2b5457675a0506903a)
The pattern of polling on a status register until a bit is set or a
timeout occurs is repeated multiple times in the driver. Mutualize the
code by introducing the nand_wait_int() helper that does wait for the
bit to flip or returns an error in case of timeout.
Change-Id: Id41d445462a0fab357d9582d0560b77a07e5ac1c
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 28f7a9d375c8bc7a30563b8d995b9baa355c7e41)
Change NFC_SEND_ADR to NFC_SEND_ADDR.
Change-Id: I7042369a3de14534a0fb3f25ebed9d5b3234e774
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 802f766994ded5afc9d89e93556011063a430e0d)
In the nand_read_buffer() step, the seed is calculated by doing a modulo
by conf->nseeds which is always zero when not using the randomizer (most
of SLC NANDs).
This situation turns out to lead to a run time freeze with certain
toolchains.
Derive this seed only when the randomizer is enabled (and conf->nseeds
logically not zero), exactly like what has been done before with an
identical situation, see commit ea3f750c73 ("nand: sunxi: Fix modulo
by zero error").
Change-Id: Ie3fdf32e1636b16a60b92ed90e965007ef29369c
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a0a984e14a41bf07f6b3f563a2a8bd22c03aea3a)
When the requested ECC strength does not exactly match the strengths
supported by the ECC engine, the driver is selecting the closest
strength meeting the 'selected_strength > requested_strength'
constraint. Fix the fact that, in this particular case, ecc->strength
value was not updated to match the 'selected_strength'.
For instance, one can encounter this issue when no ECC requirement is
filled in the device tree while the NAND chip minimum requirement is not
a strength/step_size combo natively supported by the ECC engine.
Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com>
Change-Id: I1a0f337fc5241ad6d994219979ac4c5588ab1784
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f3aff376892a5af55a090d29e53e10391f886d80)
Change-Id: I0ba60a6d86cd7f4777f91027fc9da3f4db855114
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c0ce4ceaba03fa6ddf738628344025c44fc78dd4)
NAND erase was not happening for size 1GiB or more. Erase
command was executing successfully but in actual, it was not
erasing.
This patch fixed erase issue for 1 GiB or more size nand.
Change-Id: Iee50e5a07ab1d4f65fa0c826c248864449b50ef7
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2453c695185f8fd8257f370b746acdfe5ee56408)
Make sure the user is notified instead of silently returning an error.
Change-Id: I727948d67e404a09a2b444296a3cd8189a3662ed
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit aa1ced7f09798700f3d96f39f6f5dc7d3d34cf66)
ppc4xx support was removed some time ago. Lets remove the now unused
NAND driver and all its references for this platform as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Scott Wood <oss@buserror.net>
Change-Id: I18d36aa6b1529d608acb7d39f886c3b45a791c22
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ec9c80d643a3e5ff35c5d24d675cb1feaa440c9d)
For STM32F4 and F7 SoCx family, a specific stm32.h file exists.
Some common defines are duplicated or even unused in each of
these stm32.h.
Factorize all common definition in arch/arm/include/asm/stm32f.h and keep
specific definitions in each arch/arm/include/asm/arch-stm32fx/stm32.h.
Change-Id: I63b112cc23cde9d970a29fb0fba728d34b065d1b
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2536f18bfa22eacc8d39d5b68762374f4bca8986)
This SUNXI variant SPL SPI code doesn't use either SPI or
SPL_FLASG subsystems due to size constraints and also placing
this code in drivers/mtd/spi will unnecessary build SPI_FLASH
code(if defined) which never required, hence moved to arch area.
And also renamed the file according to kconfig which resembles
proper name.
Change-Id: I0bf18e93d26bc1b80d3dfa7219a2a904ed17085a
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c2a7a7ef866f2980213fee2a4a0df60fb06db6d0)
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.
This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives:
#include <libfdt.h> -> #include <linux/libfdt.h>
#include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Change-Id: I68fd5734d6460c169fa5ee2893c57cb5d73340b6
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b08c8c4870831c9315dcae237772238e80035bd5)
Add entry for ISSI IS25LP256 part.
Change-Id: I80fbd5458f5d85b8a996dec746bf196276b9952e
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 0a84925974f26023df743d2b601ab1328a485e35)
Fixes a bug found on thuban boards, which were for 2 years in
a long-term test with varying temperatures. They showed
problems in u-boot when attaching the ubi partition:
U-Boot# run flash_self_test
Booting from nand
set A...
UBI: attaching mtd1 to ubi0
UBI: scanning is finished
data abort
pc : [<87f97c3c>] lr : [<87f97c28>]
reloc pc : [<8012cc3c>] lr : [<8012cc28>]
sp : 85f686e8 ip : 00000020 fp : 000001f7
r10: 8605ce40 r9 : 85f68ef8 r8 : 0001f000
r7 : 00000001 r6 : 00000006 r5 : 0001f000 r4 : 85f6ecc0
r3 : 00000000 r2 : 44e35000 r1 : 87fcbcd4 r0 : 87fc755b
Flags: nZCv IRQs off FIQs on Mode SVC_32
Resetting CPU ...
Reason is, that accidentially the U-Boot implementation
from __schedule_ubi_work() did not check the flag
ubi->thread_enabled and started with wearleveling work,
but ubi did not have setup all structures at this point
and crashes.
Solve this problem by splitting work scheduling and processing.
Change-Id: I0929e70c36da53b173cf135bd461bbf22f8e2e12
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f82290afc84716a16a8e300d5d17702858ba84ea)
This converts the following to Kconfig:
CONFIG_APBH_DMA
CONFIG_APBH_DMA_BURST
CONFIG_APBH_DMA_BURST8
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
[trini: Add in MMC as well]
Change-Id: I45b919ab747aa414ba23f1e165c11dd8aff44c44
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 99bec1aead5927c54f4364bfe10823a86fe0dad2)
This converts CONFIG_NAND_MXS to Kconfig.
Change-Id: I217ef77c1e7a11072e08f84d2ab4720e98df9b3f
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit c87c81186cf7e5073dbc7c5f46ad256a84f5ed22)
On detach UBI attempts to update fastmap after closing user interfaces
but at this point UBI volumes have already been free()'ed and fastmap
can no longer access these data structures.
Change-Id: I580c53b74539cd76d328e15c7c49ec54b5d67bf9
Signed-off-by: Martin Townsend <mtownsend1973@gmail.com>
Cc: hs@denx.de
Cc: kmpark@infradead.org
Cc: richard@sigma-star.at
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2d2d306f79e5ae090790fd380662f5407ccace11)
Alexey Brodkin
Stefan Roese
Carlo Caione
Marek Vasut
Rick Chen
Patrice Chotard
Ashish Kumar
Kimmo Rautkoski
Siva Durga Prasad Paladugu
Marcel Ziswiler
Jagdish Gediya
Ezequiel Garcia
Sean Nyekjaer
Eugeniy Paltsev
Mario Six
Marek Vasut
Vipul Kumar
Miquel Raynal
Petr Vorel
Liam Beguin
Jagan Teki
Masahiro Yamada
Richard Weinberger
Adam Ford
Stefan Agner
Martin Townsend