It's possible that we don't need SPL if we set CONFIG_ARM64_BOOT_AARCH32=y,
but uboot.img with FIT format is still required to be generated.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I5330f58f9ca5a18a119bdcbfd4e9e716a69b1131
It's a way to test system stability before kernel stages.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6679fbbbaa7233750b409b6b832849d8dbd36893
The RNG driver is separate from the Crypto driver.
Change-Id: I51b39e337106988d5444246a53e46c27644effb0
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
dev_read_alias_seq() used uc_drv->name compared to alias
stem string, Ethernet's alias stem uses "ethernet", which
does not match the eth-uclass driver name "eth", can not
get the correct index of ethernet alias namer. So it seems
change uclass driver name to match the alias stem is a more
reasonable way.
(cherry picked from commit 1231184caacad32c180d7e2338a645f7dfe9571a)
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I2ebbf20ae2a127456f92dc79461610b7b339c8f3
Signed-off-by: David Wu <david.wu@rock-chips.com>
rng module is not belongs to crypto driver anymore.
Change-Id: I6d837397621267edb586034ff87b82fc33a30d5b
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
rng module is not belongs to crypto driver anymore.
Change-Id: I0f2dd50e93666ba6c8a9a43fab786beb1eeb93a8
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
The current value timer_rate_hz causes a problem with function
timer_get_us() from lib time and then an issue with
readx_poll_timeout() function.
With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK
the weak functions in lib timer can be used:
- get_timer()
- __udelay()
So the specific function in this file are removed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
(cherry picked from commit 77aace579a9a84c74e99d2e86ecc08b1d9ca402b)
Change-Id: Id289de433e49d396a95e3a72acf210be3a2d910b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
For the RNG uclass we currently only have a test working on the sandbox.
Provide a command to test the hardware random number generator on
non-sandbox systems.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
(cherry picked from commit 4f24ac08afccd5f51f0b4c7023fc8cf45efe8163)
Change-Id: Icb2a9359417a8168a38e1fc009960e8c6df924e4
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Add a driver for the rng device found on rockchip platforms.
Support rng module of crypto v1 and crypto v2.
Change-Id: I5be779aa08452977965d032e366f4e36c930b12e
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
(cherry picked from commit b072d00c225e5b8147ed7444ebeae4ddd336870b)
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Add a uclass for reading a random number seed from a random number
generator device.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit a2487684003b0bc380955e1a38cdd71da3ca4366)
Change-Id: Ife2287132db695181d663653f2ceaab0e343b41f
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
The Rockchip DWC3 controller only support DRD mode (Dual Role
Device), but not support OTG mode. So if the dr_mode in DTS is
configured to OTG, then we force it to Host mode. This patch
does not affect the device function of OTG, such as rockusb.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I806623aa9b0bb8b595417755db7d9c6b6c4f38f1
This patch set the USB 2.0 PHY0 port0 and PHY1 port0 and
port1 in suspend mode to save power. And set the USB 2.0
PHY0 port0 for OTG interface still in normal mode.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I684e3bf8ce7934402e745ea7cfe110b987f5d9db
Fix compile error if enable CONFIG_SPL_FIT_SIGNATURE:
LD spl/u-boot-spl
lib/built-in.o: In function `rsa_burn_key_hash':
/home4/cjh/uboot-nextdev/lib/rsa/rsa-verify.c:591: undefined reference to `misc_otp_get_device'
/home4/cjh/uboot-nextdev/lib/rsa/rsa-verify.c:595: undefined reference to `misc_otp_read'
/home4/cjh/uboot-nextdev/lib/rsa/rsa-verify.c:661: undefined reference to `misc_otp_read'
/home4/cjh/uboot-nextdev/lib/rsa/rsa-verify.c:673: undefined reference to `misc_otp_write'
/home4/cjh/uboot-nextdev/lib/rsa/rsa-verify.c:678: undefined reference to `misc_otp_read'
/home4/cjh/uboot-nextdev/lib/rsa/rsa-verify.c:688: undefined reference to `misc_otp_write'
scripts/Makefile.spl:357: recipe for target 'spl/u-boot-spl' failed
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I48c6a2349bc10451f7c2c1f99f8b522e1244fad6
The current 4-minute data transfer timeout is misleading and broken.
Instead of such a long wait, calculate the timeout duration based on
the length of the data transfer. The current formula is the transfer
length in bits, divided by a multiplication of bus frequency in Hz,
bus width, DDR mode and converted the mSec. The value is bounded from
the bottom to 10000 mSec.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I168b6ceba917d3e621559a92a63fac78abca6bff
(cherry picked from commit 4e16f0a67d80b4ce11995b870b5d9c8d11266d0d)
The function has a little fix during upstream review, do fix to sync
with upstream.
Change-Id: I9e1c43a660b2f83395d1639aa962988ca04494e5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
1.reserve for GPT
2.kernel spinor erasesize is 64KB
Change-Id: I32a5b26f8f39b4b226ec54342ce5d8d3d71f1c4d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Joseph Chen
Jason Zhu
Jon Lin
Lin Jinhan
David Wu
Patrick Delaunay
Heinrich Schuchardt
Sughosh Ganu
William Wu
Wenping Zhang
Weiwen Chen
Jianqun Xu
Wyon Bi
Tang Yun ping