Commit Graph

3 Commits

Author SHA1 Message Date
Elaine Zhang 6bfdfc4f06 clk: rockchip: rk3399: support dual pll for vop
set the vop's parent just vpll and cpll,
set vop parent in dts node,the same as kernel setting.
i.e:
&vopb {
	status = "okay";
	assigned-clocks = <&cru DCLK_VOP0_DIV>;
	assigned-clock-parents = <&cru PLL_VPLL>;
};
&vopl {
	status = "okay";
	assigned-clocks = <&cru DCLK_VOP1_DIV>;
	assigned-clock-parents = <&cru PLL_CPLL>;
};

Change-Id: I07ab4e2837cf7fc0860e8b4d14adb8936f5cb27a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-06-28 16:35:33 +08:00
Kever Yang 5ae2fd9724 rockchip: clk: rk3399: update driver for spl
Add ddr clock setting, add rockchip_get_pmucru API,
and enable of-platdata support.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag and fix pmuclk_init() build warning:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:43 -06:00
Kever Yang 777c834fd4 dts: add support for Rockchip rk3399 soc
These files are from kernel upstream:
"649a371 Add linux-next specific files for 20160616"
with some modification need by U-Boot:
- chosen with stdout-path to uart2.
- add clock-frequency for uart2

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-25 20:46:45 -06:00