Resync from kernel-4.19:
(I5f310f9b857 clk: rockchip: rk3568: export cpll_xxx clk id for more
function)
Change-Id: I4f5ea86ed73272dc3381ba27d1c56284fa17d546
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
from kernel-4.19:
(3bd4dd9 ARM: dts: rv1126: Add CPU idle states node.)
otp and secure-otp nodes are only defined in U-Boot.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I2fcdf677bd86a477dc087d3e4986ee6cd2dfe4de
RV1109 is a SoC from Rockchip, which embedded with a
dual-core ARM Cortex-A7 and a risc-v core.
Change-Id: I0e82c6f1487bd7f2948df81055b78553c139e144
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
base on commit 54e75c20:
(clk: rockchip: rk1808: add clk ID for clk_rtc32k_frac)
Change-Id: Iac1db11af0e6c9d54e66a1d634d890ef6999c7d9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
base on commit dabd2ea:
(arm64: dts: rockchip: fix mapping address for rk1808 pmugrf)
Change-Id: I6536c03fc2c90ddf1dd8eeb626b7d03f33fdbcc9
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Make clock ids consistent with kernel.
Support more clks to set and get rate.
Add clk dump.
Change-Id: I348c98ce81ce76af9c492a30480fcb495da7ed79
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Make clock ids consistent with kernel.
support more clks to set and get rate.
add clk init.
Change-Id: I1e6b5734887e0bd5d845f1286f10eb0e3e42bc08
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
support PLL freq setting,
support bus and peri clk freq setting,
support aclk vio and dclk vop freq setting.
Change-Id: I894552c1e1bb1bd13a143e200edf289234a53c1d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The RK3288 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3288 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
implement the gmac clock set parent, but simply ignore the
others' set_rate() operation and return 0 to signal success.
Change-Id: Ic1a41634aba674001beb0e7e5ca3f7f2fa008e51
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.
Change-Id: I4963f03f6aea2c7196f33dae0bca38a432c80690
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Change-Id: I46c4f0f80b54a72acdba107ea290a45c231c3dda
Signed-off-by: Francis Fan <francis.fan@rock-chips.com>
Signed-off-by: Cody Xie <cody.xie@rock-chips.com>
support vop clk setting freq, for uboot logo display.
Change-Id: I766bdc2c3a13d0ee92f81fbd7a30b7cc87c2dceb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Change-Id: I1ff152b72a75680601f22c5b621de8b2198a6778
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit 2e4ce50d1aca35d13944f48a7e15d0b63e86eb38)
zhangqing
Joseph Chen
Finley Xiao
Jianqun Xu
Jon Lin
Yu YongZhen
Nickey Yang
Andy Yan
David Wu
Kever Yang
Jerry Xu
Francis Fan
Mark Yao