Use CONFIG_SPL_KERNEL_BOOT for thunder boot to stay the same with SPL.
Change-Id: I0d2f0a91a5f628233de1cb848519fd76b692a2af
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
add some special pll configs for better clock jitter.
Change-Id: I3484d36feb9f4b99a42a2ba532ae2015968d83ff
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
flush_dcache_all() operating on set/way is faster than
flush_cache() and invalidate_dcache_range() operating
on virtual address.
Tested: it saves about 12.5ms in rv1126 thunder-boot.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie8ba42f56e72d0d554dca3949573196ef2165bd7
Keep rv1126 support in pinctrl-rockchip.c with legency
Change-Id: I50791c3c30e6efa58d324eaef7bfc4d4aa9e440c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Put the nr_pins information to pinctrl info structure, instead of
calculating in probe.
Change-Id: I3af11d99ef4b0e30c306ebd99a2233cd0c6b97b5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Only some Soc need Schmitter feature, so move the
implementation into their own files.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 79d16e45409f928c952b6935d695cd08f9db76b3)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I41ede5737258292e27492e391cf9a981210e4a71
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 623aca88308b4f917f0465cd5dd1514ee781bee8)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Idcbb3fdf4311567c599686d52926a057d1101b6b
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 69a38f81bb55893a8555c899319305c539226a0a)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ie8f94cf1a0b33a24bb32d3de8231b7f2db51ddff
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 743a77373bfa22ca099b30d4ac88d95a2f98d1b6)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ib0de627d3aee1759965d64852bcd287785538dc0
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 956362c84b0422ea99da947feca2878193c26ade)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I409107119d557b953c904b53e657685907879a3a
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 625ab11fdae3daf346647aaba59abee804e34589)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I07caae48cd4699aa7bbddf2edf7de6863c0a58c2
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit cd8f00ce08102d2dbb350c76bbb53f7b0f804b7d)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I7aaaf9642ee7bed6a2e9f6538a053bd6e1810dd7
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 54e75702c48a9757e82cbe71176c0b5ddcf6a092)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ifdfce706e9b1cbe94300d2bed91182033f23f301
Some files have the redundant spaces, remove them.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 8541beb86daf3ce7e4be9ca67859aab3dd0daefb)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I9f621c3714260165bab0111e486a1d60ecf33c11
Some Socs use the pull-pin-default config param, need to add it.
And input-enable/disable config params are not necessary, remove it.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 0a5cc3cac96dcbb1f31c9c2a3954dad702a543c1)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Id7522a4fdd21d42d46c42e6f66b93985064fd9ab
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ibf0ba2d879904a06a2fb6722f5886a39c010a7f7
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit e7ae4cf27a6d5837cb5e868712cdaa61d3ceb5e0)
1. fix with error handle with pin with IOMUX_UNROUTED.
2. add get pin count operation
3. modify drivers/pinctrl/rockchip/Makefile
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I1a398c865eb9e9afc38c6aca5431b6546e7260a6
1. set the noc ddrtimingc0.b.wrtomwr for LPDDR4
2. set the noc ddrmode.b.mwrsize for LPDDR4
3. update the noc ddrmode.b.burstsize
4. update the controller timing for 328MHz
5. set ddr4timing to 0 except LPDDR4
6. calculate ddr4timing using *_L timing for DDR4
Change-Id: I9f8fae51a05f8547d64da262d4c69fd4edec79fb
Signed-off-by: YouMin Chen <cym@rock-chips.com>
lpddr4 reg0x107/108 is for clk driver strength.
for other type of dram this register is for A6/A8 driver strength.
Change-Id: Ia0acbe03574ad5a1a4ecdaa2c0f53cb9a45c034b
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
The SPL without thunder-boot or U-Boot needs it.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie2d8b59e35fbc2056cfbc910dae94419afcbfc09
add some special pll configs for better clock jitter.
Change-Id: I93f8cab2a995fc584322070e25bbba6067c80dbb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We misunderstood the size_src as decompressed image size.
Without this patch, the decompress can work normally, but
it wastes the time to flush data cache. Let's correct it
for thunder boot version to save boot time.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I93014ccec7814faec5abbe96b383bc1170cdb0e2
According to the spec, phy version of rv1126 is the
same as rk1808, LPX parameters need to be specified.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I75cf9db0b3763237727f3ebf3576929a3cb9cea8
Prepare to read data, then data is transmitted in background.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Iab560f7f903549a0b6c27f7e8e2ac984ae2ac75c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Enable it by set CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT to y.
Change-Id: I54db1d1b33fc9e063c05bc4aca85589b495a4db9
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
That's not correct and it breaks SMBUS-style reads and and writes for
some chips (e.g. SYR82X/SYR83X).
Stop bit should be sent only after the last message.
Change-Id: I5ded4a43ed726b7cffa35d020ef763471bd01b41
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit c9fca5ec8849b8fa16b16cece091645e7d3aa02b)
High 16-bit for numerator, Low 16-bit for denominator.
Fixes: 95f2641240 ("clk: rockchip: px30: add support clock for SCLK_I2S1")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Iafbb03ceaa7ccc178ee2a74be2fab6c2b7268ced
Using dm reset API to reset decompress module.
There seems to be some unknown cause to make the module
in abnormal state, which output the wrong decompress
data. Let's reset it before starting decompress.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic4113eec0701f83059453fa263810d31caa406eb
If the decompress module doesn't access the data through dcache,
it should add flush behavior to promise getting the real data
from dram. Otherwise it may decompress the wrong data but not
report any failure.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6570ca7dc3a60c4b5bb9fcf3ae9f1025e2c658ea
SPL don't support IRQ and U-Boot proper is not deeply care
about boot time. There is not a mechanism to support IRQ
mode now.
In addition, the decompress irq is design to catch the exceptions
but not to decompress images continuously.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I842bce530aa180d5b0a30c1d2038575e464241b8
- Support get gunzip data size from src data;
- Support sync decompress for this round;
- Support return the gunzip data size of compressed image.
- Add misc_decompress_cleanup() for waiting last decompress done.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie84b2a6174d04592110333d66667da66f98f07f6
We use it to exit charge animation while system is in runtime.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ia6bc3f7a20310f73e060418f0a0ab01ef8745b11
use ROCKCHIP_RSA to enable RSA in uboot.
use SPL_ROCKCHIP_RSA to enable RSA in spl.
Change-Id: I1c3ae3754e9dbdfe39c81b554387fe78451a9fa2
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
The default ubi part info must be corrected while the part info will
be changed when enable a/b.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I84db2e284f732f62014d3d14d99217fb707b85c0
Modify ddr support frequency to match PLL setting.
Change-Id: I1d93b2178933ada04e178bd068a8fec4ef43a4de
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Support XT26G01A, XT26G02A, XT26G04A, XT26G01B, XT26G02B
Change-Id: I447d83e5c5da8f6ba8515aab77a8039fe9cb2cc4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
fix timeout bug of crypto V2 computing large amounts of data all
at one time.
Change-Id: I6c4a3f8b0a40e95b0832244313d7e378e1e70615
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
In order to check this node by list_del_init().
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I723821d8b9fc6d899fbd5c0b830b240486a48c73
The io-domain/pmu-io-domain node always under grf/pmugrf, so get the
grf/pmugrf regmap base just from its parent device.
Change-Id: I9f7d950744b48c239a556b7fe685749cdd5f99f2
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The rockchip_pin_ctrl struct is BSS data, only memset oncetime, but the
driver maybe probed several times, the nr_pins member of struct won't
to start from 0. that will cause pinctrl driver error.
Change-Id: I3d081da8bb91573126c6ee5af345ed73c85bb7af
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Naturally, otp is written by bytes and programed just one time.
Now the rollback space is written by bit and programed several times.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I964693c5067ffdedfc0990f038f6d013a49a41a8
Parts of esmt devices are the same MFR id, and it's
reasonable.
Change-Id: I245c66ebd734ebabe89d8a6792446b80b76dd0e3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Support F50L1G41LB
Change-Id: I094a093fd07b6b2f924a58cf45375e214df796ce
Signed-off-by: Carl <xjxia@grandstream.cn>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
also update GRF_REG_FIELD for support some chip
(like rv1126) GRF's register offset over 0x10000
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Iedb281dae00f85375166915c39663e92d990b0d3
Not only does dw-hdmi use these functions, but others
need to use them, such as inno-hdmi.
Change-Id: I1ced6e30b7634511fecbbfb39c24ede78894dd1d
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Use CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE to select dram type.
Use the same define with arch/arm/include/asm/arch-rockchip/sdram.h (0 for
DDR4, 2 for DDR2, 3 for DDR3, 5 for LPDDR2, 6 for LPDDR3, 7 for LPDDR4).
Change-Id: I982db49c1881f6975afd4ba48f88ee3dd9286d3e
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
If some child info->prefix are the same, try to
distinguish them by parent addr.
Example:
pmic@20, pmic@1a...
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I504cd887e232bb309d8e1790f6d55910172d08b5
If CONFIG_ROCKCHIP_THUNDER_BOOT=y, it will enable ddr fast boot.
Change-Id: Ia43039dd1247ebb937aaa8b6d9a9103df2dfe1f5
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
1.add DECOM_AXI_STAT to test decompress whether is in idle
2.correct the misc_decompress_is_complete return value
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I904d9909ade709fb479893325dd6c0b3d47d5908
vop full need to do rb swap when deal with rgb888/bgr888;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I60fac72b21720fcf4f406c56fe7d9dc21ebf7635
Rename CONSOLE_SERIAL_SKIP_INIT to DEBUG_UART_ALWAYS_MODE for
easy understand.
Select this to always use debug UART, skip complicated
console UART register.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I3c265840bde015fe5fd7c73d959ba0538297b7c2
This function prepares to read data without confirming completed.
We can use it to prefetch data and run other process.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I76116c25dfdb7559b80a0216c414189e85409a3e
1.Check map table block address overflow
2.Reinit map table original value
Change-Id: I4450b5a6856e38e2624da9db31d5eb98de7f5696
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
since kernel set rk312x win1 to show kernel logo, so here sync with
kernel config.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I3ed562526cd6f61359bef1567c7f2ea57149435d
Vop WIN with multi-region support(win2 of rv1126)
should enable the bit.
Change-Id: I3e2c4165e0d2c597ab839829f9cbed6a1e37c59a
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
In order to prevent physical memory from being written oversize,
limit the decompressed buffer size, user can assign a size to
decompress, the reserved destination buffer size is a choice
Change-Id: I8723c5ec8d58ec1d443c5607987941cf67cf1a01
Signed-off-by: Simon Xue <xxm@rock-chips.com>
1.Logical offset should not mix with map address
2.Format with nand_read_skip_bad
Change-Id: I0e5adec374ce4de437e4ce7368caec4c7c07e83b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Change-Id: I2718843dd4646b7450c36e84cc16e6440c718959
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8d38a8459b0de45f5ff41f3e11c278a5cf395fd0)
The current brcmnand driver is based on 4.18 linux kernel which uses
mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from
old kernel which does not use this new API and expect nand_chip.ecc.layout
structure to be set. This cause nand_scan_tail function running into a bug
check if the device has a different oob size than the default ones.
This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7
that supports the ecc layout struture and replaces the mtd_set_ooblayout
method
Change-Id: I31aec45275decfb03af2829c744c3dda0e261d12
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e365de90517ba4686d7a88417b1a729f5891d376)
This is done by default in the raw NAND core (nand_base.c) but was
missing in the SPI-NAND core. Without these two lines the ecc_strength
and ecc_step_size values are not exported to the user through sysfs.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
Change-Id: I37f29616e1522d9ce9e9d7ec18a473c73e1d1551
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Currently when marking a block, we use spinand_erase_op() to erase
the block before writing the marker to the OOB area. Doing so without
waiting for the operation to finish can lead to the marking failing
silently and no bad block marker being written to the flash.
In fact we don't need to do an erase at all before writing the BBM.
The ECC is disabled for raw accesses to the OOB data and we don't
need to work around any issues with chips reporting ECC errors as it
is known to be the case for raw NAND.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
Change-Id: Ieaa72162810105bf5d62caf2efc16a1c2ef89d6d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
When writing the bad block marker to the OOB area the access mode
should be set to MTD_OPS_RAW as it is done for reading the marker.
Currently this only works because req.mode is initialized to
MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for
req.mode != MTD_OPS_AUTO_OOB.
Fix this by explicitly setting req.mode to MTD_OPS_RAW.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schrempf@kontron.de
Change-Id: Id415efc0cd8d61d97d98e0340729f8bc60fc28cf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
For reading and writing the bad block markers, spinand->oobbuf is
currently used as a buffer for the marker bytes. During the
underlying read and write operations to actually get/set the content
of the OOB area, the content of spinand->oobbuf is reused and changed
by accessing it through spinand->oobbuf and/or spinand->databuf.
This is a flaw in the original design of the SPI NAND core and at the
latest from 13c15e07eedf ("mtd: spinand: Handle the case where
PROGRAM LOAD does not reset the cache") on, it results in not having
the bad block marker written at all, as the spinand->oobbuf is
cleared to 0xff after setting the marker bytes to zero.
To fix it, we now just store the two bytes for the marker on the
stack and let the read/write operations copy it from/to the page
buffer later.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schrempf@kontron.de
Change-Id: I5a47981f004c60d753da382ef6d683a7da1e436b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Linux has good support for Toshiba SPI-NAND, so lets import it.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Tested-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Change-Id: I70a328bf28c7e8740d818958faf749016dd9ca77
(cherry picked from commit 89127104848cea38bac5d40e3d6973fc203e2df6)
This Soc is different from the previous Socs, need to
define eqos_config, and follow the dwc_eth_qos driver
process.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4a1c1605dd46ed31fb7ca15c7c26572739f636ec
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ib60f306cb9e8abec9557e92a6d04d76a7071b9ea
The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I214b0b2fbe04a139de911435c4abf224264f5495
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I313674274fc2eddb7717ba76c537cd668d6a492b
When using rgmii Gigabit mode, the wait_for_bit_le32()
reset method resulting in RX can not receive data, after
this patch, works well.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Id1d2405397d0c2f59b7bf1e341cdf66b023e4226
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ic845d330465c1bb8f7868fb188e5bf30c865b9b5
If there are definitions for eqos_start_clks and eqos_stop_clks,
then call these callback function.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Id5ffc944a2c066d78a784aeb28ecb846b53e52fd
For Rockchip, need to obtain the current link speed to
configure the tx clocks, (for example, in rgmii mode,
1000M link: 125M, 100M link: 25M, 10M link is 2.5M rate)
and then enable gmac. So after the adjust_link(), before
the start gamc, this intermediate stage needs to configure
the clock according to the current link speed.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I9a46da28abca0544cb0a56b0a0574e2fd1de0c52
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I952ac6cc6a4278c887b530bd6d387752358c89a8
After moving to eqos_ops, if eqos_config is defined
outside file, can not export interface() definition,
only export eqos_ops struct defined in dwc_eth_qos.c.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibc60f49f36bb2011454370ed7fcc6d9db3b34d9f
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I428c7158c113143a7e51296705fabde6f05eb0f6
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia1d19c61fb8a2c8540b3dfda53b6aeb3b72acb7f
Implement the read_rom_hwaddr callback to load MAC address from fuse
for imx8m platforms.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4204948ae6a0408f7d642007d27923a3c6941562
Implement the callbacks to get phy mode interface and txclk
rate configuration.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I0a5265347936c1bc821c175eea1698d2624d4873
Add dwc eqos for imx support.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I49127be057a49e6b45e37f940d523d808c20343b
Update eQoS and fec ethernet drivers to support shared MDIO framework
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iaf5f3ca585190c6469b68195aaea2499242a0096
For dual ethernet controllers, the HW design may connect ETH phys to
one MDIO ports. So two different ethernet drivers have to share MDIO bus.
Since two ethernet drivers are independent, we can't ensure their probe
order.
To resolve this problem, introduce an eth phy generic driver and uclass.
After eth-uclass binds, we search the mdio node and binds the phy node
with the eth-phy-generic driver.
When one eth driver get its phy device, the parent of phy device will
probe prior than phy device. So this ensure the eth driver ownes the
MDIO bus will be probed before using its MDIO.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ice83493e9e1caf3842f9ce0c129e29ad46cc0532
Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as
stand-alone devices. Useful in particular for systems that support
DM_ETH and have a stand-alone MDIO hardware block shared by multiple
Ethernet interfaces.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I8e106f4360aa46289e0ed551f8f685cad9dc6269
The DMA may attempt to write a DMA descriptor in the ring while it is
being updated. By writing the DMA descriptor buffer address to 0, it
is assured the DMA will not use such a buffer and the buffer can be
updated without any interference.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: If70a57f195c146d571de20385b55ff75f7dea7db
This patch prevents an issue where the RX packet might have been
accessed by the CPU, which now has cached data from the packet in
the caches and possibly various write buffers, and these data may
be evicted from the caches into the DRAM while the buffer is also
written by the DMA.
By invalidating the buffer after the CPU accessed it and before the
DMA populates the buffer, it is assured that the buffer will not be
corrupted.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6271396aad6abac3fb11e5e742a3b2c9e7cc355b
The current code polls the RX desciptor ring for new packets by reading
the RX descriptor status. This works by accident, as the RX descriptors
are often in non-cacheable memory. However, the driver does support use
of RX descriptors in cacheable memory.
This patch adds a missing RX descriptor invalidation, which assures the
CPU will read a fresh copy of the RX descriptor instead of a cached one.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia05e8a43d707088bc3699b7d00434c8d12d2692f
Currently the code only flushes the first RX descriptor, not every entry
in the RX descriptor ring. Fix this, to make sure the DMA engine can pick
the RX descriptors correctly.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7a37f8a1fd51b2b7ca4fb557885d711ebd72c49c
This code programs the next descriptor in the TX descriptor ring into
the hardware as the last valid TX descriptor. The problem is that if
the currenty descriptor is the last one in the array, the code will
not wrap around correctly and use TX descriptor 0 again, but instead
will use TX descriptor at address right past the TX descriptor ring,
which is the first descriptor in the RX ring.
Fix this by adding the necessary wrap-around.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iaf0f5dba76c232af1cbef628c099aaf43542757d
The RX descriptor field 3 should contain only OWN and BUF1V bits before
being used for receiving data by the DMA engine. However, right now, if
the descriptor was already used for receiving data and is being cleared,
the field 3 is only modified and the aforementioned two bits are ORRed
into the field. This could lead to a residual dirty bits being left in
the field 3 from previous transfer, and it generally does. Fully set the
field 3 instead to clear those residual dirty bits.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I5b116fa58de65b3958c3ddd87f6c182c532b9542
Add management of property "reg" to configure @ of phy and
also "max-speed" property to specify maximum speed in Mbit/s
supported by the device
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6ecabcffc4782f1e641d8ee1021f6c3caf360707
Add management of property "reset-gpios" in the node identified by
"phy-handle" to configure any GPIO used to reset the PHY.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia7dfcafc2e2f90a5ca48205dd2562fb62a3d6d84
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to
phy_connect(). Passing 0 used to work before be accident, but does no
longer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibc8a780b8a7e1be6f827ca901d0b1f2b384ca627
Align the board and driver prototype for board_interface_eth_init
to avoid execution issue (the interface_type parameter is defined
as int or phy_interface_t).
To have a generic weak function (it should be reused by other driver)
I change the prototype to use directly udevice.
This prototype is added in netdev.h to allow compilation check
and avoid warning when compiling with W=1 on file
board/st/stm32mp1/stm32mp1.c
warning: no previous prototype for 'board_interface_eth_init'\
[-Wmissing-prototypes]
int board_interface_eth_init(int interface_type, ....
^~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7301e49ef8e51ecdde0629a69d7bcc07465952d0
This patch solves many warnings when compiling with W=1:
warning: no previous prototype for '....' [-Wmissing-prototypes]
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ice01d9d56324b450f313a4a74e5039581e20a08e
Synopsys GMAC 4.20 is used. And Phy mode for eval and disco is RMII
with PHY Realtek RTL8211 (RGMII)
We also support some other PHY config on stm32mp157c
PHY_MODE (MII,GMII, RMII, RGMII) and in normal,
PHY wo crystal (25Mhz and 50Mhz), No 125Mhz from PHY config
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ie696f22dd260f6712c61744c60dc9d5a64737a5a
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by several means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. Direct access for C45 PHYs and C22 PHYs when accessing the reachable
DEVADs.
3. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I53a73274b6386f8a510b590a0f7ce1923f7b5528
The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iae1c8e2414b655639c42f7098a097c6a0a1e5792
Now the UCLASS_ETH device "node" field is owerwritten by some network drivers in
case of Ethernet PHYs which are linked to UCLASS_ETH device using
"phy-handle" DT property and when Ethernet PHY driver needs to read some
additional information from DT. In such cases following happens (in
general):
- network drivers
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
<-- phydev is connected to dev which is UCLASS_ETH device
if (priv->phy_of_handle > 0)
dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
<-- phydev->dev->node is overwritten by phy-handle DT node
- PHY driver in .config() callback
int node = dev_of_offset(dev);
<-- PHY driver uses overwritten dev->node
const void *fdt = gd->fdt_blob;
if (fdtdec_get_bool(fdt, node, "property"))
...
As result, UCLASS_ETH device can't be used any more for DT accessing.
This patch adds additional ofnode node field to struct phy_device which can
be set explicitly by network drivers and used by PHY drivers, so
overwriting can be avoided. Also add helper function phy_get_ofnode()
which will check and return phy_device->node or dev_ofnode(phydev->dev) for
backward compatibility with existing drivers.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I31fcf01cfb19894bc90d198d9138c1fd3e25802e
Add clk_valid() to check for optional clocks are valid.
Call clk_valid() in test/dm/clk.c and add relevant test routine to
sandbox clk tests.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I78b1edea1f8ef54d3aa3f7610d39d79dd994d1bf
As dmac aclk comes from hclk pdbus, dmac pclk comes frome pclk pdbus,
dmac aclk should be an integer multiple of dmac pclk and the same
parent with dmac pclk. so let hclk pdbus and pclk pdbus only come from
gpll.
Change-Id: Idd2f362fcf160352dcb4577ad8a13b4dbec7c65f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Since v2.80a, dwmmc controller introduced the card write threshold for
HS200 & HS400 mode. So CardThrCtl can be supported during write operation, not
only read operation.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I7f345660107c2978d2f874d36f2dffd2acdfbcb6
The v2 gpio controller add write enable bit for some register,
such as data register, data direction register and so on.
This patch support v2 gpio controller by redefine the read and
write operation functions.
Change-Id: I2adbcca06a37c48e6f494b89833cd034ba0dae29
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Do 'gpio status -a' will cause system crash, due to the pins number
error for gpio4 (last gpio controller).
Test on RV1126 IOTEST board, which has only 8 pins for GPIO4.
Change-Id: I4150abd0ca97bc4f3043eb7fcae2287818125031
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This reverts commit ef473e3642.
We merged this commit while we didn't notice that this driver gets
init voltage from legacy "rockchip,pwm_voltage = <...>", but regulator
uclass gets it from "regulator-init-microvolt = <...>". so we have to
revert this commit to compatible the legacy one.
Change-Id: I52606d9a9268659d3d77f7d29d1eed1d80b30b1e
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
The blk_dread will occor error if the image is packed with multiple
firmwares, for example boot.img, when nand or spi nand have bad block.
So call mtd_blk_map_table_init to remap part address to make sure
reading correct data.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Icebc6b1c5a10758efa615424d0706b9ed6ec23ad
In general we should avoid calling malloc() and free() repeatedly in
U-Boot lest we turn it into tianocore. In SPL this can make SPI flash
unusable since free() is often a nop and allocation space is limited.
In any case, these seems no need for malloc() since the number of bytes
is very small, perhaps less than 8.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: d13f5b254a (spi: Extend the core to ease integration of SPI
memory controllers)
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ca2abb75a086d8b0bdb51689f331ba8f1a146379)
Change-Id: Ia76abf7491780b1984eb81c6c78796bcc0141095
Add check if exec_op is set before calling it.
At the moment it is called unconditionally, which leads to a crash if it
is not set correctly.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 567a3eb7956f98af4ed065499898c6d0ac6443c7)
Change-Id: Ie9fdf0cbee364fc33965e3234d7457702bd0120f
Spetial patch for GD devices cause u-boot SPI Nand MTD bad
supporting for GD, and the u-boot mainline haven't synchronize
with Linux.
reference to following Linux commit:
commit f1541773af49ecd1edae29c8ac0775253a0b0760
Author: Chuanhong Guo <gch981213@gmail.com>
Date: Sat Feb 8 15:43:50 2020 +0800
mtd: spinand: rework detect procedure for different READ_ID operation
Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
3. opcode + 1 dummy byte. Found in other currently supported chips.
Original implementation was for variant 1 and let detect function
of chips with variant 2 and 3 to ignore the first byte. This isn't
robust:
1. For chips of variant 2, if SPI master doesn't keep MOSI low
during read, chip will get a random id offset, and the entire id
buffer will shift by that offset, causing detect failure.
2. For chips of variant 1, if it happens to get a devid that equals
to manufacture id of variant 2 or 3 chips, it'll get incorrectly
detected.
This patch reworks detect procedure to address problems above. New
logic do detection for all variants separatedly, in 1-2-3 order.
Since all current detect methods do exactly the same id matching
procedure, unify them into core.c and remove detect method from
manufacture_ops.
Change-Id: If60d0281eb963486639d5b4ce1939ad2b219c8d6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
When a CPU enters a low power state, the registers ICC_IGRPEN1_EL1 is lost.
It need to re-initialise.
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I62d9eed2b29190134d95ebd153f21aa764c4ab3b
1.set auto_wakeup_screen_invert to 1 and set auto_off_screen_interval to 0.
2.set auto_screen_off_timeout to 1.
2.press power key to turn on screen.
3.screen will not be turned off at this time.
Change-Id: Ifc92f23a38d8ba0da4f6e37625b4114edb42f6a8
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Fix the size of the buffer allocated to store the in-memory BBT.
This bug was previously hidden by a different bug, that was fixed in
commit e4fd10db8b8 ("mtd: nand: Fix nanddev_neraseblocks()").
Fixes: ed99f7731 ("mtd: nand: Add core infrastructure to deal with NAND devices")
Change-Id: I365fdfe053ef352661a832b33a232cbb18e81be6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.SPI Nand MTD partition bad block will not be detected if the address
isn't begin with the partition first block.
2.To avoid this problem, we should use map partition block address to
get right data.
3.It's compatible if the map table isn't initialed.
Change-Id: I11858b9b30a8fffecdbad804b1bad7b247b51d23
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
ioctl() should return error code but not data.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ica1242619ed59728acbeda7db493e5710f410a17
1.SPI Nand MTD partition bad block will not be detected if the address
isn't begin with the partition first block.
2.To avoid this problem, we should use map partition block address to
get right data.
3.It's compatible if the map table isn't initialed.
Change-Id: I11858b9b30a8fffecdbad804b1bad7b247b51d23
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
ioctl() should return error code but not data.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ica1242619ed59728acbeda7db493e5710f410a17
fix: ioctl() should return error code but not capability.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8030a1842692697f32f87e765ce3d68d1adb1c11
Puting the generic function declaration together that the
caller don't need care too much about different header file.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ib37d1550e5a747d8f18e30c428ea8f613f9cc006
This patch updates the RC driver to accommodate the new framework
Signed-off-by: Lei Chen <lei.chen@rock-chips.com>
Change-Id: I3ff2b5844ce5f1776ac2f94b3cbd42eb5d73cc41
That snor_info_packet is SPI Nor information placed in IDB header
area, each progress can parse it to get flash information.
Change-Id: I63621a5b92c2fb85b588365d9415fbb40eece8a3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Switch to the device model and support mtd.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Idfb60cec7a375254a423677b1c3f1da4be954eb5
The misc attach different device. We use the misc_mode to show
different device's capability.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ibce5bb0465e452a7e783c5859f1e8ab2bfd8b0c5
SPL is the stage early than atf/op-tee that psci sysreset
is not supported.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I46b988b3776638265bf8f374a10f9027d1ebc90f
Providing a mininum adc key driver for SPL, which does not
depend on key uclass, but ADC uclass is still required.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I80f861780acd9c47d345b95762a4dd39d19ea6fc
Regulator should be a option but not mandory for dm adc.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I5fdda2d76dd8ce75673732cc0563d7a18be211e2
Tang Yun ping
Jon Lin
Jason Zhu
Elaine Zhang
Joseph Chen
Jianqun Xu
David Wu
YouMin Chen
Simon Xue
Nickey Yang
Sandy Huang
Wyon Bi
Vasily Khoruzhick
Lin Jinhan
Algea Cao
Shunqing Chen
Andy Yan
Simon Glass
William Zhang
Robert Marko
Finley Xiao
Ye Li
Fugang Duan
Alex Marginean
Marek Vasut
Patrick Delaunay
Christophe Roullier
Carlo Caione
Pankaj Bansal
Grygorii Strashko
Fabrice Gasnier
Bernhard Messerklinger
shengfei Xu
Lei Chen
Yifeng Zhao