The i2c5 xfer went wrong because of io-domain was not right
and was configured correctly in uboot to ensure that kernel
was right before initializing the io-domain driver.
Change-Id: Ic2f94952f7a851dc5b781af9f31bba2562b5a2b5
Signed-off-by: David Wu <david.wu@rock-chips.com>
Before the patch, we get gpio index(0,1,2..) depends on gpio
fdt node name, such as: gpio0@..., gpio1@..., etc.
But from RK3568, we add gpio alias to indicate gpio index
information and index is removed from gpio node name, ie:
gpio@fdd60000, gpio@fe740000, etc.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I56e45941f9572fbc6a5a5916896e12f6eff9dcf3
In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.
Change-Id: Ib93da14b5309ec094b952e03f8514817910fedfa
Signed-off-by: William Wu <william.wu@rock-chips.com>
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the
OTG port of PHY0 support OTG mode with charging detection
function, they are similar to previous Rockchip SoCs.
However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ia33d3de222a6c7f263290f4098d0a5e557a9d568
1.Support SPI Nand and SLC Nand in mtd case;
2.Only support address and length erasesize aligned case;
Change-Id: I8e76274677c153fb61616ebf320e1b86d5060439
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
In this mode, uart debug is initialized depends on
configuration from pre-loader or CONFIG_UART_DEBUG_.
The serial is not care about dts "stdout-path" and
not register into console framework any more. It's
nice to use pre-loader serial and make serial easy
to configure.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If4c68229d76b6f1710a35e3ef9a2a91cb306fa9c
This patch auto detect BW16 constitute by byte0 and byte2 or
byte0 and byte3.
Change-Id: I22a8fa70db1d996573004320196c0892d5380f64
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
RK3568 only support cpu interface system registers access.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie89380e49ee61afe57560dcc4eba6233f2aca3f2
Different platform has different phy IP, distinguish them by
the compatible data.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Iaf78eee8abe7e9cd91c1edcd42fd65a611c3b0be
This adds the necessary data for handling otp on the rv1126.
Change-Id: Ie78ad04861ee8dca506f0bb7b851570b360694de
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
after system test, 32bit interface use pageclose can improve
performance, 16bit interface not improve.
Change-Id: Iecac7aae1e5f8ec4f162200d80be16f1b91180f5
Signed-off-by: CanYang He <hcy@rock-chips.com>
The mtd blk need mtd erase size to check bad block.x
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If1bca0ce442599be41f3fd12638529018885f3e0
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Add "fasboot getvar snapshot-update-status" support and
prevent erase/wipe of userdata/metadata when virtual A/B
merge status is MERGING or SNAPSHOTTED (+source slot !=
current slot).
Signed-off-by: Dayao Ji <jdy@rock-chips.com>
Change-Id: Ibb6ea5778b78b2601178f489d6efcee60d5d0a49
Use CONFIG_SPL_KERNEL_BOOT for thunder boot to stay the same with SPL.
Change-Id: I0d2f0a91a5f628233de1cb848519fd76b692a2af
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
add some special pll configs for better clock jitter.
Change-Id: I3484d36feb9f4b99a42a2ba532ae2015968d83ff
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
flush_dcache_all() operating on set/way is faster than
flush_cache() and invalidate_dcache_range() operating
on virtual address.
Tested: it saves about 12.5ms in rv1126 thunder-boot.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie8ba42f56e72d0d554dca3949573196ef2165bd7
Keep rv1126 support in pinctrl-rockchip.c with legency
Change-Id: I50791c3c30e6efa58d324eaef7bfc4d4aa9e440c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Put the nr_pins information to pinctrl info structure, instead of
calculating in probe.
Change-Id: I3af11d99ef4b0e30c306ebd99a2233cd0c6b97b5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Only some Soc need Schmitter feature, so move the
implementation into their own files.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 79d16e45409f928c952b6935d695cd08f9db76b3)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I41ede5737258292e27492e391cf9a981210e4a71
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 623aca88308b4f917f0465cd5dd1514ee781bee8)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Idcbb3fdf4311567c599686d52926a057d1101b6b
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 69a38f81bb55893a8555c899319305c539226a0a)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ie8f94cf1a0b33a24bb32d3de8231b7f2db51ddff
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 743a77373bfa22ca099b30d4ac88d95a2f98d1b6)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ib0de627d3aee1759965d64852bcd287785538dc0
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 956362c84b0422ea99da947feca2878193c26ade)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I409107119d557b953c904b53e657685907879a3a
As the common set_mux func(), implement the feature at the own file
for each Soc.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 625ab11fdae3daf346647aaba59abee804e34589)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I07caae48cd4699aa7bbddf2edf7de6863c0a58c2
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit cd8f00ce08102d2dbb350c76bbb53f7b0f804b7d)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I7aaaf9642ee7bed6a2e9f6538a053bd6e1810dd7
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 54e75702c48a9757e82cbe71176c0b5ddcf6a092)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ifdfce706e9b1cbe94300d2bed91182033f23f301
Some files have the redundant spaces, remove them.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 8541beb86daf3ce7e4be9ca67859aab3dd0daefb)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I9f621c3714260165bab0111e486a1d60ecf33c11
Some Socs use the pull-pin-default config param, need to add it.
And input-enable/disable config params are not necessary, remove it.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 0a5cc3cac96dcbb1f31c9c2a3954dad702a543c1)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Id7522a4fdd21d42d46c42e6f66b93985064fd9ab
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ibf0ba2d879904a06a2fb6722f5886a39c010a7f7
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit e7ae4cf27a6d5837cb5e868712cdaa61d3ceb5e0)
1. fix with error handle with pin with IOMUX_UNROUTED.
2. add get pin count operation
3. modify drivers/pinctrl/rockchip/Makefile
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I1a398c865eb9e9afc38c6aca5431b6546e7260a6
1. set the noc ddrtimingc0.b.wrtomwr for LPDDR4
2. set the noc ddrmode.b.mwrsize for LPDDR4
3. update the noc ddrmode.b.burstsize
4. update the controller timing for 328MHz
5. set ddr4timing to 0 except LPDDR4
6. calculate ddr4timing using *_L timing for DDR4
Change-Id: I9f8fae51a05f8547d64da262d4c69fd4edec79fb
Signed-off-by: YouMin Chen <cym@rock-chips.com>
lpddr4 reg0x107/108 is for clk driver strength.
for other type of dram this register is for A6/A8 driver strength.
Change-Id: Ia0acbe03574ad5a1a4ecdaa2c0f53cb9a45c034b
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
The SPL without thunder-boot or U-Boot needs it.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie2d8b59e35fbc2056cfbc910dae94419afcbfc09
add some special pll configs for better clock jitter.
Change-Id: I93f8cab2a995fc584322070e25bbba6067c80dbb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We misunderstood the size_src as decompressed image size.
Without this patch, the decompress can work normally, but
it wastes the time to flush data cache. Let's correct it
for thunder boot version to save boot time.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I93014ccec7814faec5abbe96b383bc1170cdb0e2
According to the spec, phy version of rv1126 is the
same as rk1808, LPX parameters need to be specified.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I75cf9db0b3763237727f3ebf3576929a3cb9cea8
Prepare to read data, then data is transmitted in background.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Iab560f7f903549a0b6c27f7e8e2ac984ae2ac75c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Enable it by set CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT to y.
Change-Id: I54db1d1b33fc9e063c05bc4aca85589b495a4db9
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
That's not correct and it breaks SMBUS-style reads and and writes for
some chips (e.g. SYR82X/SYR83X).
Stop bit should be sent only after the last message.
Change-Id: I5ded4a43ed726b7cffa35d020ef763471bd01b41
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit c9fca5ec8849b8fa16b16cece091645e7d3aa02b)
High 16-bit for numerator, Low 16-bit for denominator.
Fixes: 95f2641240 ("clk: rockchip: px30: add support clock for SCLK_I2S1")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Iafbb03ceaa7ccc178ee2a74be2fab6c2b7268ced
Using dm reset API to reset decompress module.
There seems to be some unknown cause to make the module
in abnormal state, which output the wrong decompress
data. Let's reset it before starting decompress.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic4113eec0701f83059453fa263810d31caa406eb
If the decompress module doesn't access the data through dcache,
it should add flush behavior to promise getting the real data
from dram. Otherwise it may decompress the wrong data but not
report any failure.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6570ca7dc3a60c4b5bb9fcf3ae9f1025e2c658ea
SPL don't support IRQ and U-Boot proper is not deeply care
about boot time. There is not a mechanism to support IRQ
mode now.
In addition, the decompress irq is design to catch the exceptions
but not to decompress images continuously.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I842bce530aa180d5b0a30c1d2038575e464241b8
- Support get gunzip data size from src data;
- Support sync decompress for this round;
- Support return the gunzip data size of compressed image.
- Add misc_decompress_cleanup() for waiting last decompress done.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie84b2a6174d04592110333d66667da66f98f07f6
We use it to exit charge animation while system is in runtime.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ia6bc3f7a20310f73e060418f0a0ab01ef8745b11
use ROCKCHIP_RSA to enable RSA in uboot.
use SPL_ROCKCHIP_RSA to enable RSA in spl.
Change-Id: I1c3ae3754e9dbdfe39c81b554387fe78451a9fa2
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
The default ubi part info must be corrected while the part info will
be changed when enable a/b.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I84db2e284f732f62014d3d14d99217fb707b85c0
Modify ddr support frequency to match PLL setting.
Change-Id: I1d93b2178933ada04e178bd068a8fec4ef43a4de
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Support XT26G01A, XT26G02A, XT26G04A, XT26G01B, XT26G02B
Change-Id: I447d83e5c5da8f6ba8515aab77a8039fe9cb2cc4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
fix timeout bug of crypto V2 computing large amounts of data all
at one time.
Change-Id: I6c4a3f8b0a40e95b0832244313d7e378e1e70615
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
In order to check this node by list_del_init().
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I723821d8b9fc6d899fbd5c0b830b240486a48c73
The io-domain/pmu-io-domain node always under grf/pmugrf, so get the
grf/pmugrf regmap base just from its parent device.
Change-Id: I9f7d950744b48c239a556b7fe685749cdd5f99f2
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The rockchip_pin_ctrl struct is BSS data, only memset oncetime, but the
driver maybe probed several times, the nr_pins member of struct won't
to start from 0. that will cause pinctrl driver error.
Change-Id: I3d081da8bb91573126c6ee5af345ed73c85bb7af
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Naturally, otp is written by bytes and programed just one time.
Now the rollback space is written by bit and programed several times.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I964693c5067ffdedfc0990f038f6d013a49a41a8
Parts of esmt devices are the same MFR id, and it's
reasonable.
Change-Id: I245c66ebd734ebabe89d8a6792446b80b76dd0e3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Support F50L1G41LB
Change-Id: I094a093fd07b6b2f924a58cf45375e214df796ce
Signed-off-by: Carl <xjxia@grandstream.cn>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
also update GRF_REG_FIELD for support some chip
(like rv1126) GRF's register offset over 0x10000
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Iedb281dae00f85375166915c39663e92d990b0d3
Not only does dw-hdmi use these functions, but others
need to use them, such as inno-hdmi.
Change-Id: I1ced6e30b7634511fecbbfb39c24ede78894dd1d
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Use CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE to select dram type.
Use the same define with arch/arm/include/asm/arch-rockchip/sdram.h (0 for
DDR4, 2 for DDR2, 3 for DDR3, 5 for LPDDR2, 6 for LPDDR3, 7 for LPDDR4).
Change-Id: I982db49c1881f6975afd4ba48f88ee3dd9286d3e
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
If some child info->prefix are the same, try to
distinguish them by parent addr.
Example:
pmic@20, pmic@1a...
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I504cd887e232bb309d8e1790f6d55910172d08b5
If CONFIG_ROCKCHIP_THUNDER_BOOT=y, it will enable ddr fast boot.
Change-Id: Ia43039dd1247ebb937aaa8b6d9a9103df2dfe1f5
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
1.add DECOM_AXI_STAT to test decompress whether is in idle
2.correct the misc_decompress_is_complete return value
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I904d9909ade709fb479893325dd6c0b3d47d5908
vop full need to do rb swap when deal with rgb888/bgr888;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I60fac72b21720fcf4f406c56fe7d9dc21ebf7635
Rename CONSOLE_SERIAL_SKIP_INIT to DEBUG_UART_ALWAYS_MODE for
easy understand.
Select this to always use debug UART, skip complicated
console UART register.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I3c265840bde015fe5fd7c73d959ba0538297b7c2
This function prepares to read data without confirming completed.
We can use it to prefetch data and run other process.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I76116c25dfdb7559b80a0216c414189e85409a3e
1.Check map table block address overflow
2.Reinit map table original value
Change-Id: I4450b5a6856e38e2624da9db31d5eb98de7f5696
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
since kernel set rk312x win1 to show kernel logo, so here sync with
kernel config.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I3ed562526cd6f61359bef1567c7f2ea57149435d
Vop WIN with multi-region support(win2 of rv1126)
should enable the bit.
Change-Id: I3e2c4165e0d2c597ab839829f9cbed6a1e37c59a
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
In order to prevent physical memory from being written oversize,
limit the decompressed buffer size, user can assign a size to
decompress, the reserved destination buffer size is a choice
Change-Id: I8723c5ec8d58ec1d443c5607987941cf67cf1a01
Signed-off-by: Simon Xue <xxm@rock-chips.com>
1.Logical offset should not mix with map address
2.Format with nand_read_skip_bad
Change-Id: I0e5adec374ce4de437e4ce7368caec4c7c07e83b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Change-Id: I2718843dd4646b7450c36e84cc16e6440c718959
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 8d38a8459b0de45f5ff41f3e11c278a5cf395fd0)
The current brcmnand driver is based on 4.18 linux kernel which uses
mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from
old kernel which does not use this new API and expect nand_chip.ecc.layout
structure to be set. This cause nand_scan_tail function running into a bug
check if the device has a different oob size than the default ones.
This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7
that supports the ecc layout struture and replaces the mtd_set_ooblayout
method
Change-Id: I31aec45275decfb03af2829c744c3dda0e261d12
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e365de90517ba4686d7a88417b1a729f5891d376)
This is done by default in the raw NAND core (nand_base.c) but was
missing in the SPI-NAND core. Without these two lines the ecc_strength
and ecc_step_size values are not exported to the user through sysfs.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
Change-Id: I37f29616e1522d9ce9e9d7ec18a473c73e1d1551
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Currently when marking a block, we use spinand_erase_op() to erase
the block before writing the marker to the OOB area. Doing so without
waiting for the operation to finish can lead to the marking failing
silently and no bad block marker being written to the flash.
In fact we don't need to do an erase at all before writing the BBM.
The ECC is disabled for raw accesses to the OOB data and we don't
need to work around any issues with chips reporting ECC errors as it
is known to be the case for raw NAND.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: stable@vger.kernel.org
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
Change-Id: Ieaa72162810105bf5d62caf2efc16a1c2ef89d6d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
When writing the bad block marker to the OOB area the access mode
should be set to MTD_OPS_RAW as it is done for reading the marker.
Currently this only works because req.mode is initialized to
MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for
req.mode != MTD_OPS_AUTO_OOB.
Fix this by explicitly setting req.mode to MTD_OPS_RAW.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schrempf@kontron.de
Change-Id: Id415efc0cd8d61d97d98e0340729f8bc60fc28cf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Elaine Zhang
David Wu
Joseph Chen
William Wu
Jason Zhu
Yifeng Zhao
Jianqun Xu
Ren Jianing
Jon Lin
YouMin Chen
Tang Yun ping
Lin Jinhan
Finley Xiao
CanYang He
Dayao Ji
Simon Xue
Nickey Yang
Sandy Huang
Wyon Bi
Vasily Khoruzhick
Algea Cao
Shunqing Chen
Andy Yan
Simon Glass
William Zhang