Commit Graph

13700 Commits

Author SHA1 Message Date
Joseph Chen e6b2bd8785 irq: irq-gpio-switch: correct usage of strstr()
Fix gpio interrupt register with wrong gpio bank.

(Fixes: 8db677370c irq: irq-gpio-switch: add gpio alias name support)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ia60e55a134cfab19ed015796486417e0699bd087
2020-12-18 18:02:39 +08:00
Shunqing Chen 3c3ec66903 fuel gauge: rk817/rk809: fix get rsoc error
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: Id946d56c9aafef87bb864218155e1b2353991140
2020-12-18 14:43:48 +08:00
Wenping Zhang e79e208579 video/rk_eink: fix screen display stripes after WF_TYPE_RESET update.
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
Change-Id: Id406c1103a0deea3e3ab9abcb8664e1ccc098520
2020-12-16 06:53:58 +00:00
Guochun Huang c3a1ac4926 video/drm: inno_mipi_phy: Add support for rk3568
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ie6e5810ad3614e28a540b3bbfc071cf36362da79
2020-12-15 17:41:28 +08:00
Joseph Chen 094465a906 power: charge animation: disable timer while uninit timer
Otherwise the time is still working in kernel if there is no
one to update it, which always wakeups system suspend.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic2291b26730557c50fb8cbd505d05b40bb582c74
2020-12-15 17:38:48 +08:00
Zorro Liu cd44409e4e drivers: video: rk_eink: update cmdline vcom parameter
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: I80ac52356380bf4194d7115036634ffae35d21ce
2020-12-15 16:19:53 +08:00
Jason Zhu cf432719d2 misc: rockchip-otp: support rk3568
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I21be09b06f7ac3a0f75e47e59ec094d6e254d05d
2020-12-15 16:19:19 +08:00
Jon Lin 4bf17e940b mtd: mtd_blk: Support mtd_dwrite in spl
Change-Id: I495ca5498fae9f03f6042cb074c9c8c3f590eea5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-13 19:25:20 +08:00
Jon Lin 8ff9c29cc8 mtd: spinor: Add more mtd information
1.erasesize_shift, erasesize_mask
2.it's useful for mtd_blk.c

Change-Id: I0bd184fc86637849fbd079f9f539387465a07b8f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-13 18:00:31 +08:00
Wenping Zhang 255e57518a power: charge animation: add eink charging display.
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
Change-Id: Id9d84a27ae2bbc8746e99ed01a96c53e2335a2b6
2020-12-10 17:51:14 +08:00
Wenping Zhang 93a7515a89 video/rk_eink: add rockchip eink support.
Signed-off-by: Wenping Zhang <wenping.zhang@rock-chips.com>
Change-Id: I39e92ee00690ea1be274b1abd94d54284ef36898
2020-12-10 17:51:14 +08:00
Elaine Zhang 0a04fb5062 clk: rockchip: rk3568: support rkvdec clk setting
Change-Id: Ic63b3c8ecbefcdf551d646ebb40521e6b521610b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-12-10 15:26:42 +08:00
Jon Lin a792c7e0c5 mtd: spinand: Support new devices
HYF1GQ4UDACAE, HYF4GQ4UAACBE

Change-Id: I7abcc925ccdf8be5507a8b584b58c6b03a78962c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 19:27:55 +08:00
Jon Lin 4cab706e7f mtd: spinand: Support new devices
FM25S01

Change-Id: I1c7eab8799b0a381b7fa32584e608c3a115d83e6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 19:27:48 +08:00
Jon Lin 0659623d62 mtd: spinand: Support new devices
FS35ND02G-S3Y2, FS35ND04G-S2Y2

Change-Id: Idc74c823fc707ba4dbeac359c4f6ca0a7e3ee778
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 19:27:34 +08:00
Jon Lin ad6355f7d7 mtd: spinand: Support new devices
XT26G01C

Change-Id: If7147ebd12a993de86b335824d8c6e9d8ea06d52
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 16:00:38 +08:00
Jon Lin 266cba03bb mtd: spinand: Supoprt new devices
TC58CVG2S0HRAIJ

Change-Id: I4412a9208fe8f22053dbb74d1cb362b19e13a18a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 15:07:38 +08:00
Jon Lin 55efc32aea mtd: spinand: Supoprt new MXIC devices
MX35UF1GE4AC, MX35UF2GE4AC

Change-Id: I064e9116c565e2ea3b92432e9c68864d47a7567c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 14:57:38 +08:00
Jon Lin 5fe488ff12 mtd: spinand: Support new devices
HYF2GQ4UAACAE, HYF2GQ4UHCCAE

Change-Id: I1b36ca507984d2794375a6c1bce409d749495c62
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-09 14:53:06 +08:00
Jason Zhu 990fd51c55 misc: rockchip-otp: extract the difference in each chips
We use function spl_rockchip_otp_start & spl_rockchip_otp_stop to
realize the different of each chip's otps, such as mask area and
secure config.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I3b5d0377d78e5c2ed6e8ed52a89cadefc4994be1
2020-12-08 17:37:39 +08:00
Shunqing Chen 3b02c9fe3a power: fg_cw201x: replace fdt functions
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: Id03c367e619444f5f76ecbb36f831e09959d2888
2020-12-07 02:34:36 +00:00
Jason Zhu 77e56285c1 clk: rockchip: rk3568: support set sdmmc0 clock
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ic7bdfce9a9551649e053f58b6d9219e73e6afed5
2020-12-07 09:24:24 +08:00
zhangqing f6d2779458 clk: rockchip: rk3568: support more clk setting
support cpll_xxx settings.

Change-Id: I2735f6abe0fb02828b7ace76b58a60757199cab8
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
2020-12-07 09:22:55 +08:00
Jason Zhu d62fa58224 mmc: sdhci: rockchip: reset the clock phase
Reset the clock phase when the frequency is lower than 52MHz.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I49c50779ab5e1103d815cd2be1a7c9603cea397a
2020-12-07 09:20:43 +08:00
Jon Lin 3c70338210 rkflash: Support new spinor
1.Support XT25F256BSFIGU, P25Q32SH-SSH-IT
2.Fix PUYA devices property

Change-Id: I6c5ff381770508962f8ed16189d03385f511d84f
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-07 09:19:54 +08:00
Jon Lin a097a4fc3a rkflash: Support spinor prog_addr_lines
Convenient for spinor detection

Change-Id: Id9e09de26ffa978f18a97d8f0555c70ee0baa22c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-07 09:19:54 +08:00
Jon Lin 49eba1a38a rkflash: Support sfc DLL api
Change-Id: Ibe8cd0d1e72e8dc871466dcb1014e6817b184e80
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-12-07 09:19:54 +08:00
Yifeng Zhao b3621a1078 spl: zftl: fix L04A and L05B boot fail issue
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Icdc93ce7d8948c3c12f28aef08c98df4b3aa3166
2020-12-03 15:08:50 +08:00
Yifeng Zhao 84dc46da6a drivers: rknand: update nand flash drivers
1. support samsung 14nm 8GB NAND FLASH.
2. support ymtc 64L 32GB NAND FLASH.
3. support toshiba 15nm 8GB NAND FLASH.
4. support rk3568

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I01c9eb698c1ae829e6a2858c2664d62cf0851ab7
2020-11-30 10:03:05 +08:00
Yifeng Zhao e18e709024 drivers: rknand: add nand flash drivers for spl
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I21c449226f57f2ff05fdcf241dde014062634cb5
2020-11-27 20:06:23 +08:00
Joseph Chen d7965d03e2 pinctrl: rockchip: add SPL support
CONFIG_OF_LIVE is always available in SPL and U-Boot.

Use CONFIG_IS_ENABLED(OF_LIVE) to unwind as CONFIG_OF_LIVE
in U-Boot and CONFIG_SPL_OF_LIVE in SPL.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I980579d54850ca7655b464688ba9e6bd35f24250
2020-11-27 14:05:18 +08:00
Shunqing Chen 038c1ecaa2 power: charge animation: energy enough auto exit uboot charge
Change-Id: Ifa94783869c7cb35f819f3700c82bac7d00a7b05
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
2020-11-26 15:23:46 +08:00
Shunqing Chen 00d11ef213 pmic: rk8xx: support power key config from dts
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: I4b2def4e5b171b2b46f26695e9cabec8a7b496e2
2020-11-26 11:51:28 +08:00
Jon Lin e336ce4ee5 mtd: spinand: Add foresee devices
Change-Id: I115ea19030edc2e83e877621f055555b481f98db
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-11-26 09:10:57 +08:00
Jason Zhu 65bd598f41 clk: rockchip: rk3568: set the ACLK_BUS to 150MHz in spl
Since the mcu uses the ACLK_BUS clock and 150MHz is need as
default clock rate.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I60c4603fa0c0b45667c6583992ea461fed18fcf5
2020-11-24 17:13:18 +08:00
Lin Jinhan 00fa57d80d driver: crypto: mask CRYPTO_SYNC_LOCKSTEP_INT_ST flag
This flag maybe abnormal trigger.

Change-Id: Id398d1e8636c28b8cc42d950cafa5e2731a41b62
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
2020-11-24 16:02:35 +08:00
Lin Jinhan 7eea182341 crypto: rockchip: support rk3568 without hwrng in crypto
Change-Id: I557a05e0336fe6b80d903a48a2d088f165a4eeca
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
2020-11-24 16:02:35 +08:00
David Wu 7ef28ab639 i2c: rockchip: Clean ipd status if i2c transfer error
If there was an i2c transfer error like iomux error,
should clean the ipd status, it might cause kernel i2c
irq error handing.

[    0.690749] rk3x-i2c fdd40000.i2c: irq in STATE_IDLE, ipd = 0x10

Change-Id: Ia127edada535288e9b984d6dc0dff813e6152eff
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-24 14:43:46 +08:00
Jon Lin 22edf95882 mtd: spinand: Support W25N02KV
Change-Id: Iaf4a50ce7bb0bb9978a05d339a34763445c09c84
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-11-20 20:54:39 +08:00
Jon Lin b833c879cf rkflash: Support new spi flash
1.Support W25N02KVZEIR
2.Support GD25B512MEYIG, MX25U51245G

Change-Id: Ia0181aa3fc6cbf17e2b0abd43dea80b5d9848d88
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-11-20 20:31:21 +08:00
Jianqun Xu dbff1ed621 gpio: rockchip: get gpio bank from pinctrl device
Change-Id: I0dd2bc1b61bfdfe8edfd79b3a794522499eaae5c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-19 14:50:05 +08:00
Jianqun Xu e9c98b3baf gpio: rockchip: fix get gpio mux operation error return
Change-Id: Ia225ae3acea2d2d2347870b3d6a20c4a7d22e7e9
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-19 14:50:05 +08:00
Jianqun Xu 8273b391c5 pinctrl: rockchip: a pin unrouted is invalid
Change-Id: I706b23277f33768fc7c8bcfd06e6417fe3e8a0db
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-19 14:50:05 +08:00
Elaine Zhang fdd74c3220 clk: rockchip: rk3568: support ebc clk setting/getting rate
Change-Id: Iecac8e56b2b5615b54c8969767053b6282fe6fb8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-19 14:48:18 +08:00
Jason Zhu 661bcdfeff mtd: mtd_blk: add mtd_blk_map_fit() to create map for fit image
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I0d0195f455ee9afb32676510fc077fe63ae5c7ad
2020-11-18 16:10:55 +08:00
Zhihuan He 379e9cabde drivers: ram: rk3308: add sdram_rk3308.c build
Change-Id: I43079e6709d6eeb691eb73786bba7920c081b9c9
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2020-11-17 20:56:28 +08:00
Finley Xiao b85730d9e9 clk: rockchip: rv1126: Fix mask bits for gmac src clks
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I7f81a3e7586dcb85511502d3a329ac1cba7ccc8a
2020-11-17 14:46:27 +08:00
Zhihuan He 8ec8d58eeb drivers: ram: rockchip: add rk3308 sdram driver
Change-Id: I96160af2095ba21b440c6d3789349d8cbc4fea75
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2020-11-16 20:40:52 +08:00
Zhihuan He b86c816ccb drivers: ram: rockchip: rv1108: clean up the code
Change-Id: I3446805fd9c320ddd49b9cb12df82943057ed9ee
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
2020-11-16 20:39:39 +08:00
Ren Jianing 7329ce5782 phy: rockchip-inno-usb2: fix some issues for rk3568 usb2 phy
This patch fixes the following issues for rk3568 usb2 phy.

1. Set utmi opmode to normal mode for rk3568 usb phy when usb
phy enter suspend mode via usb phy grf. It can help to avoid
the DM/DP floating and the line state be detected as 2'b11.

2. Fix the offset of INT_STATUS_CLR. It can help to avoid
triggering the linestate irq constantly.

Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ic108e116d1473341b61743ec4244bc034a95f501
2020-11-16 15:59:44 +08:00
Elaine Zhang 802c460a72 clk: rockchip: rk3568: support ppll setting 200M
Change-Id: If5d4d1994956a8e18f3208a22daee6efca80950b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-16 15:05:05 +08:00
David Wu 458cbae45a power: rockchip-io-domain: Use private write for rk3568
The i2c5 xfer went wrong because of io-domain was not right
and was configured correctly in uboot to ensure that kernel
was right before initializing the io-domain driver.

Change-Id: Ic2f94952f7a851dc5b781af9f31bba2562b5a2b5
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-16 11:45:51 +08:00
Joseph Chen 8db677370c irq: irq-gpio-switch: add gpio alias name support
Before the patch, we get gpio index(0,1,2..) depends on gpio
fdt node name, such as: gpio0@..., gpio1@..., etc.

But from RK3568, we add gpio alias to indicate gpio index
information and index is removed from gpio node name, ie:
gpio@fdd60000, gpio@fe740000, etc.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I56e45941f9572fbc6a5a5916896e12f6eff9dcf3
2020-11-14 15:32:03 +08:00
David Wu e4e3f4318d net: gmac_rockchip: Add rmii support for rv1126
Change-Id: I89401b89ff8fd3d9cca754d6f1c05dc76ef2cda6
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-14 15:23:48 +08:00
William Wu 3b2dd5de37 usb: dwc3: do not use 3.0 clock when operating in 2.0 mode
In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.

Change-Id: Ib93da14b5309ec094b952e03f8514817910fedfa
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-14 12:05:13 +08:00
Jason Zhu 60238d95dc mmc: sdhci: rockchip: change tapnum to 16
According to the test hadware testing.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I2750a7de9f79807256800868ae53d3fe4a23b2f1
2020-11-14 11:55:39 +08:00
Yifeng Zhao 007849d805 drivers: rockusb: add new idb feature for rk3568
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Iee5ed01bb336a5b5994381fc8e734da3b87329fe
2020-11-12 20:12:17 +08:00
Yifeng Zhao 8d74d6b7d3 drivers: mmc: rockchip: rk3568: config rx clock no inverter for hs200
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I426a5c3ee0899fbd54711e13550310f77f8abd3e
2020-11-11 19:48:46 +08:00
Jianqun Xu fcff2851be power: io-domain: rockchip: fix rk3568 grf offset
Change-Id: I1045ce0d942ea57e325bdf3b8aa4bc8c9023d9e8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-10 17:15:52 +08:00
Jianqun Xu 836c6892fa pinctrl: rockchip: fix RK3568 for pull set
Change-Id: I9fa739d65caf54067f8c61142ced44f9ad9d7313
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-10 17:15:52 +08:00
Elaine Zhang 801ca42bf6 clk: rockchip: rk3568: fix up the vpll register address
Fix up the error description of TRM.

Change-Id: Ie95482efea4e78505d361b5377ff4a23826d69e3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-10 10:20:20 +08:00
Ren Jianing e475bd5dfd phy: rockchip-inno-usb2: add usb2 phy support for rk3568
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the
OTG port of PHY0 support OTG mode with charging detection
function, they are similar to previous Rockchip SoCs.

However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.

Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ia33d3de222a6c7f263290f4098d0a5e557a9d568
2020-11-09 19:39:27 +08:00
Yifeng Zhao 28b3b131e9 drivers: mmc: rockchip: fix phy dll config for hs200
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ie72f2414eca2856102e0a477668ec2729396cd25
2020-11-09 16:10:02 +08:00
Elaine Zhang d41e2874c4 clk: rockchip: rk3568: emmc support 52MHz
Change-Id: I54841ec5c7a5030bbbf9fa5b6b6fdc742250a127
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-08 20:28:41 +08:00
Elaine Zhang d01aebd267 clk: rockchip: rk3568: emmc support 400KHz
Change-Id: I1b16a4ad2e67749e63eb1506c6c1462db3e6abbd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-11-08 19:15:43 +08:00
Jon Lin a80fd39692 drivers: rkflash: Support new devices
MT29F2G1ABA, F50L2G41XA, W25Q128JVSIM, ZB25LQ128, FM25Q64-SOB-T-G

Change-Id: Idf09d96161130d4741e046acd9d520683c37213e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-11-06 14:09:54 +08:00
Jon Lin e66d4537db gadget: rockusb: Support rkusb_do_erase_force
Change-Id: Ia18c5a8414411044a72858d83ccddec63ac83e70
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-11-05 17:01:02 +08:00
Jon Lin 338697c52f mtd: mtd_blk: Support mtd_derase
1.Support SPI Nand and SLC Nand in mtd case;
2.Only support address and length erasesize aligned case;

Change-Id: I8e76274677c153fb61616ebf320e1b86d5060439
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-11-03 15:36:16 +08:00
YouMin Chen 547ad455e4 drivers: ram: rockchip: add rk3568 sdram_init for build only
Change-Id: I09a83b3192f4b332aad37f709949011f173a3dac
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2020-11-03 10:54:39 +08:00
Joseph Chen 407f6521ad serial: Kconfig: default y for DEBUG_UART_ALWAYS
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie40ee20335c4aaafe8e31c32438b78de41bc01fd
2020-11-02 20:47:30 +08:00
Joseph Chen 034db99592 dm: serial: support always use uart debug mode
In this mode, uart debug is initialized depends on
configuration from pre-loader or CONFIG_UART_DEBUG_.

The serial is not care about dts "stdout-path" and
not register into console framework any more. It's
nice to use pre-loader serial and make serial easy
to configure.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If4c68229d76b6f1710a35e3ef9a2a91cb306fa9c
2020-11-02 18:34:22 +08:00
Joseph Chen 6a1649e26d core: node: remove unused API
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I797cb2f594865ab9310651183bf98b8112fe429e
2020-11-02 18:34:21 +08:00
Joseph Chen 8c22eae691 dm: serial/16550: rollback to upstream version
rollback to: 02234e4 UPSTREAM: usbtty: fix typos

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I84296fad2b06823afc77477ef4ef11a2f801960a
2020-11-02 18:34:21 +08:00
Tang Yun ping 1040f70ad7 rockchip: rv1126: tpl: add ddr3 16bit support
This patch auto detect BW16 constitute by byte0 and byte2 or
byte0 and byte3.

Change-Id: I22a8fa70db1d996573004320196c0892d5380f64
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
2020-10-30 18:07:30 +08:00
Lin Jinhan c48f1acf4a crypto: rockchip: modify crypto hash cache support for crypto v1&v2
Change-Id: I6e0604bf02908269ab021714378b66ed712fdc06
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
2020-10-30 09:24:49 +08:00
Joseph Chen 73a2b1f652 driver: fpga: add rockchip support
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I52b089453383f9b48693c1cae3e0a97a5cf2339f
2020-10-29 15:20:08 +08:00
Joseph Chen 275a49e3fb irq: gicv3: use cpu interface system registers for gicc read/write
RK3568 only support cpu interface system registers access.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie89380e49ee61afe57560dcc4eba6233f2aca3f2
2020-10-28 21:23:07 +08:00
Joseph Chen 3582f7fa15 ram: Kconfig: select RKPARM_PARTITION by RAMDISK_RO
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Idb6ff31bf8ca4f9bf9a8fb5f0fb447236a9f8e76
2020-10-28 21:23:07 +08:00
Jason Zhu b7b235505b mmc: sdhci: support new phy IP
The new phy IP is designed by rockchip.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I5a84bcc6fff7aaf0bc848cdb70b78a57f471e51e
2020-10-28 15:03:46 +08:00
Jason Zhu 05f3b0ab30 mmc: sdhci: clean up the phy code
Different platform has different phy IP, distinguish them by
the compatible data.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Iaf78eee8abe7e9cd91c1edcd42fd65a611c3b0be
2020-10-28 15:03:46 +08:00
Elaine Zhang 392d4cef34 clk: rockchip: rk3568: update the clk config
modify the cpll and gpll register.
support Hpll set/get rate.

Change-Id: I46b372078435bc70a34d1402d43ce2431110ddbd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-10-26 16:25:37 +08:00
Finley Xiao a4c57e8a07 rockchip: otp: Add support for rv1126
This adds the necessary data for handling otp on the rv1126.

Change-Id: Ie78ad04861ee8dca506f0bb7b851570b360694de
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2020-10-23 15:06:11 +08:00
Jianqun Xu 230491661d io-domain: rockchip: add rk3568 support
Change-Id: Ic3a984043e82bd65957239acc25de79e00e1a6b8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-10-23 15:02:15 +08:00
Jianqun Xu 3f4af2112b pinctrl: rockchip: add rk3568 support
Change-Id: Ie8c3d6f6a3909ab481241b98d3af55b26c38accc
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-10-23 15:02:15 +08:00
CanYang He e8885e2486 drivers: ram: rv1126: dram 32bit interface use pageclose
after system test, 32bit interface use pageclose can improve
performance, 16bit interface not improve.

Change-Id: Iecac7aae1e5f8ec4f162200d80be16f1b91180f5
Signed-off-by: CanYang He <hcy@rock-chips.com>
2020-10-23 15:01:23 +08:00
YouMin Chen da1862e965 drivers: ram: rv1126: fix the timing about noc burstpenalty
Change-Id: I1ce56c57f8798dfc4fbefd68d47fbe97de6c390a
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2020-10-23 15:01:00 +08:00
Elaine Zhang 417bebc456 clk: rockchip: rk3568: Add clock driver
Add basic clock for rk3568 which including cpu, bus, mmc,
i2c, pwm, gmac ...clocks init.

Change-Id: I4119f10897d06befa4a39198b3724dc515d416e3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-10-22 19:39:19 +08:00
Joseph Chen c3723ef337 clk: rockchip: rk3399: support crypto clk set/get in SPL
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I159d062320ca523e8dc4f0dcce94a619692481f3
2020-10-22 16:37:49 +08:00
Jon Lin 6524556d8d mtd: mtd_blk: Fix the way to get Nand mtd_info
Change-Id: I6e47180db41242a92ac74083d5984bcb06d92e9c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-10-19 11:00:29 +08:00
Yifeng Zhao 6f8d5ecc09 spl: nand: add mtd erase size config for mtd blk
The mtd blk need mtd erase size to check bad block.x

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If1bca0ce442599be41f3fd12638529018885f3e0
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-10-16 17:57:43 +08:00
Jon Lin 3ac03e839f mtd: spinand: Support FM25S02A
Change-Id: I855a01500977285c4b8eb09ec1c013a4cdb5636e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-10-15 16:02:18 +08:00
Jon Lin 9f568152b6 rkflash: Fix last data block vpn has been modify issue
Change-Id: Ie3aa7140c368693ddd18a53225975ec2fd6ce141
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-10-10 14:54:28 +08:00
Dayao Ji 40a6a2cba2 fastboot: add virtual A/B feature support
Add "fasboot getvar snapshot-update-status" support and
prevent erase/wipe of userdata/metadata when virtual A/B
merge status is MERGING or SNAPSHOTTED (+source slot !=
current slot).

Signed-off-by: Dayao Ji <jdy@rock-chips.com>
Change-Id: Ibb6ea5778b78b2601178f489d6efcee60d5d0a49
2020-09-23 19:01:12 +08:00
Jon Lin e091dc9d13 mtd: mtd_blk: Map table length round up to erase size
Change-Id: I5f615d37a572ce0d8ceb8d6d6b76983fc61e316b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-17 15:20:49 +08:00
Jason Zhu 51ceae363d mtd: mtd_blk: support map bad block table in spl
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I48112628812b948e4ab5a34362c8ada12b00471e
2020-09-17 15:20:49 +08:00
Jon Lin 2ac88c1bbc rkflash: Check bad block mark in spare 1st and 2nd byte
Change-Id: I60bb761d1f7a015c76939db165c53bf53bd514cf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-17 14:40:02 +08:00
Jon Lin 03d86fc3c0 mtd: spinand: Support FM25S01A
Change-Id: I805cbf0e8bc47cd9bd94fd296dbaf46921490f15
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-16 12:58:33 +08:00
Jon Lin f28847a81d rkflash: Simplify SPI Nand flash table
1.Simplify SPI Nand flash table
2.Support new SPI Nand devices
3.Format coding styles

Change-Id: Ie7beae2de5b2165ce7f727aa6eab18d726d0dedc
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-16 08:39:00 +08:00
Jon Lin 4d72219b9d rkflash: Remove SFC reset in initial progress
Only when the host work wrong, run SFC reset.

Change-Id: Ia2c7f30e4e93203250dc378f2704942d99d73c55
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-16 08:38:37 +08:00
Jon Lin b66d41c240 mtd: spinand: Support hyf devices
Support HYF1GQ4UPACAE, HYF1GQ4UDACAE

Change-Id: I9b8022d9320150d587b443cfa4cdc7495267795e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-16 08:37:57 +08:00
Tang Yun ping 958e04de67 rockchip: rv1126: tpl: thunder boot use SPL_KERNEL_BOOT
Use CONFIG_SPL_KERNEL_BOOT for thunder boot to stay the same with SPL.

Change-Id: I0d2f0a91a5f628233de1cb848519fd76b692a2af
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
2020-09-16 08:37:30 +08:00
Jon Lin 247c5a81b3 mtd: spinand: Add initial support for the MX35LF4GE4AD
Change-Id: Ib1228650e76dc82bc86fb28472616d0fefb269bf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-15 09:42:28 +08:00
Jon Lin d30345d690 mtd: spinand: Add initial support for the MX35LF2GE4AD
Change-Id: Iab488487f9937d31cf419757988a4152f359e62b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-12 20:41:43 +08:00
Jon Lin 65c356141d spi: rockchip_sfc: Limit io rate to 100MHz
Change-Id: Icec10dbe65d5bbef72b858447aa15e848084712b
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-08 17:51:24 +08:00
Jon Lin 853fc11fcc blk: Add BLK_MTD_CONT_WRITE tag
Change-Id: I72537387912d5c981dbe205c0d0c1864fa42a555
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-08 17:51:23 +08:00
Jason Zhu 4d62a7e032 blk: remove unused code
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ib43223baa7d335f6810f714fd64c40cd314b0185
2020-09-07 14:53:06 +08:00
Elaine Zhang 62be0c2c53 clk: rockchip: rk3368: support get pll config by table
add some special pll configs for better clock jitter.

Change-Id: I3484d36feb9f4b99a42a2ba532ae2015968d83ff
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-09-04 14:22:54 +08:00
Joseph Chen c9f753f3de misc: rockchip decompress: use flush_dcache_all() before decompress
flush_dcache_all() operating on set/way is faster than
flush_cache() and invalidate_dcache_range() operating
on virtual address.

Tested: it saves about 12.5ms in rv1126 thunder-boot.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie8ba42f56e72d0d554dca3949573196ef2165bd7
2020-09-02 16:35:16 +08:00
Jon Lin d38748a7d2 mtd: spinand: Support DS35X2GA
Change-Id: I05e3a0d28983cf24a8a7ba0aee23e434cda4a1a9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-01 14:44:03 +08:00
Jon Lin f1b20f5a45 rkflash: Support FS35ND02G-S3Y2
Change-Id: Ifd62df6188c09fc9fccf4a38bd7c856bc8061d80
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-09-01 14:43:56 +08:00
Jianqun Xu 72832ab675 pinctrl: rockchip: add rk3308 support
Change-Id: Id2a34aa7984ee00da2bf78e55f38cf268a2ce8f3
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-08-31 16:03:47 +08:00
Jianqun Xu e20d80255b pinctrl: rockchip: add rk1808 support
Change-Id: Iac6b15651e19b7eaf6dd18339f6de6d65a3dd1ff
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-08-31 16:03:47 +08:00
Jianqun Xu 92b1d31aeb pinctrl: rockchip: add rv1126 support
Keep rv1126 support in pinctrl-rockchip.c with legency

Change-Id: I50791c3c30e6efa58d324eaef7bfc4d4aa9e440c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-08-31 16:03:47 +08:00
Jianqun Xu b8d3e6ff7d pinctrl: rockchip: set mux route in core driver
Change-Id: Iccc880b150b1cea3cef9d2a84d14a0e82ce5c5cf
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-08-31 16:03:47 +08:00
Jianqun Xu 3624458ab0 pinctrl: rockchip: put nr_pins to pinctrl info structure
Put the nr_pins information to pinctrl info structure, instead of
calculating in probe.

Change-Id: I3af11d99ef4b0e30c306ebd99a2233cd0c6b97b5
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-08-31 16:03:47 +08:00
David Wu 5635c457ec UPSTREAM: pinctrl: rockchip: Also move common set_schmitter func into per Soc file
Only some Soc need Schmitter feature, so move the
implementation into their own files.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 79d16e45409f928c952b6935d695cd08f9db76b3)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: I41ede5737258292e27492e391cf9a981210e4a71
2020-08-31 16:03:47 +08:00
David Wu b8a0fe4c87 UPSTREAM: pinctrl: rockchip: Clean the unused type and label
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 623aca88308b4f917f0465cd5dd1514ee781bee8)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: Idcbb3fdf4311567c599686d52926a057d1101b6b
2020-08-31 16:03:47 +08:00
David Wu cfe427fe38 UPSTREAM: pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' pull
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 69a38f81bb55893a8555c899319305c539226a0a)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: Ie8f94cf1a0b33a24bb32d3de8231b7f2db51ddff
2020-08-31 16:03:47 +08:00
David Wu 05a5688e53 UPSTREAM: pinctrl: rockchip: Split the common set_pull() func into per Soc
As the common set_mux func(), implement the feature at the own file
for each Soc.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 743a77373bfa22ca099b30d4ac88d95a2f98d1b6)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: Ib0de627d3aee1759965d64852bcd287785538dc0
2020-08-31 16:03:47 +08:00
David Wu 79899a49f9 UPSTREAM: pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' drive strength
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 956362c84b0422ea99da947feca2878193c26ade)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: I409107119d557b953c904b53e657685907879a3a
2020-08-31 16:03:47 +08:00
David Wu 681441e641 UPSTREAM: pinctrl: rockchip: Split the common set_drive() func into per Soc
As the common set_mux func(), implement the feature at the own file
for each Soc.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 625ab11fdae3daf346647aaba59abee804e34589)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: I07caae48cd4699aa7bbddf2edf7de6863c0a58c2
2020-08-31 16:03:47 +08:00
David Wu aa570f0140 UPSTREAM: pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' iomux
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit cd8f00ce08102d2dbb350c76bbb53f7b0f804b7d)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: I7aaaf9642ee7bed6a2e9f6538a053bd6e1810dd7
2020-08-31 16:03:47 +08:00
David Wu 5f55bbd7d6 UPSTREAM: pinctrl: rockchip: Split the common set_mux() into per Soc
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 54e75702c48a9757e82cbe71176c0b5ddcf6a092)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: Ifdfce706e9b1cbe94300d2bed91182033f23f301
2020-08-31 16:03:47 +08:00
David Wu 16f7081913 UPSTREAM: pinctrl: rockchip: Remove redundant spaces
Some files have the redundant spaces, remove them.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 8541beb86daf3ce7e4be9ca67859aab3dd0daefb)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: I9f621c3714260165bab0111e486a1d60ecf33c11
2020-08-31 16:03:47 +08:00
David Wu 8fa6c06288 UPSTREAM: pinctrl: rockchip: Add pull-pin-default param and remove unused param
Some Socs use the pull-pin-default config param, need to add it.
And input-enable/disable config params are not necessary, remove it.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 0a5cc3cac96dcbb1f31c9c2a3954dad702a543c1)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: Id7522a4fdd21d42d46c42e6f66b93985064fd9ab
2020-08-31 16:03:47 +08:00
David Wu 49b3d5d5ff UPSTREAM: pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.

Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

Change-Id: Ibf0ba2d879904a06a2fb6722f5886a39c010a7f7
2020-08-31 16:03:47 +08:00
David Wu f2e4e921f0 UPSTREAM: pinctrl: rockchip: Add common rockchip pinctrl driver
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit e7ae4cf27a6d5837cb5e868712cdaa61d3ceb5e0)

1. fix with error handle with pin with IOMUX_UNROUTED.
2. add get pin count operation
3. modify drivers/pinctrl/rockchip/Makefile

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I1a398c865eb9e9afc38c6aca5431b6546e7260a6
2020-08-31 16:03:47 +08:00
Jianqun Xu 9f32e0d2ec gpio: rockchip: handle error code from pinctrl
Change-Id: Iac48b2302da562d0c204884d9eb3f763c2071c9f
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-08-31 16:03:47 +08:00
YouMin Chen 8e4f57b962 drivers: ram: rv1126: modify the dram side DS and ODT for fsp_param
Change-Id: I1080edf76073f9387e7211b8333bf086f26a09d2
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2020-08-31 15:33:52 +08:00
YouMin Chen 38b16f0834 drivers: ram: rv1126: fix the timing about noc and controller
1. set the noc ddrtimingc0.b.wrtomwr for LPDDR4
2. set the noc ddrmode.b.mwrsize for LPDDR4
3. update the noc ddrmode.b.burstsize
4. update the controller timing for 328MHz
5. set ddr4timing to 0 except LPDDR4
6. calculate ddr4timing using *_L timing for DDR4

Change-Id: I9f8fae51a05f8547d64da262d4c69fd4edec79fb
Signed-off-by: YouMin Chen <cym@rock-chips.com>
2020-08-31 15:33:52 +08:00
Tang Yun ping a5033de0ca rv1126: ddr: fix bug of ca driver strength setup
lpddr4 reg0x107/108 is for clk driver strength.
for other type of dram this register is for A6/A8 driver strength.

Change-Id: Ia0acbe03574ad5a1a4ecdaa2c0f53cb9a45c034b
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
2020-08-31 15:33:52 +08:00
Jon Lin 14ce3c6d83 mtd: spinand: Support GD5F1GQ5UExxG
Change-Id: I5f494ce09eed8c28bd2cb10bac5ec7d9113bac50
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-08-27 17:42:11 +08:00
Joseph Chen 446ef41c12 clk: rockchip: rv1126: always support decompress clock get/set
The SPL without thunder-boot or U-Boot needs it.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie2d8b59e35fbc2056cfbc910dae94419afcbfc09
2020-08-21 17:49:13 +08:00
Simon Xue 5db33a7101 misc: rockchip_decompress: set default dclk to 400MHz
Change-Id: Ie64c1d7fd25ae2e570a06141c9942faeaadcc09c
Signed-off-by: Simon Xue <xxm@rock-chips.com>
2020-08-21 14:47:29 +08:00
Elaine Zhang 7c7fff393f clk: rockchip: rk3288: support get pll config by table
add some special pll configs for better clock jitter.

Change-Id: I93f8cab2a995fc584322070e25bbba6067c80dbb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-20 15:09:48 +08:00
Joseph Chen 8353750512 misc: decompress: wait complete before stop for sync
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ia70003e9fe2f27b6834324edabae095b6b9c21b7
2020-08-20 15:04:37 +08:00
Joseph Chen 9f59c154c4 misc: rockchip decompress: support invalidate dcache
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I668fc041083c1547357d0556cb483b6ab2f58b5a
2020-08-20 15:04:37 +08:00
Joseph Chen e1e885d399 misc: decompress: correct size_src and size_dst usage
We misunderstood the size_src as decompressed image size.

Without this patch, the decompress can work normally, but
it wastes the time to flush data cache. Let's correct it
for thunder boot version to save boot time.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I93014ccec7814faec5abbe96b383bc1170cdb0e2
2020-08-20 15:04:37 +08:00
Jon Lin a7ff7f48d1 mtd: spi-nand: Support TC58CVG0S3HRAIJ and TC58CVG1S3HRAIJ
Change-Id: I11d36cc2d17b4d8ae59d405b0177ec34f74bb704
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-08-20 14:48:36 +08:00
Nickey Yang a3c5f2d549 video/drm: inno_mipi_phy: adjust timings for rv1126
According to the spec, phy version of rv1126 is the
same as rk1808, LPX parameters need to be specified.

Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I75cf9db0b3763237727f3ebf3576929a3cb9cea8
2020-08-20 10:06:29 +08:00
Sandy Huang eee28ceac9 drm/rockchip: clearly to point out error log
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I9848cdaadcb9aa6b9ccb40f7179a000a1bc6cc00
2020-08-13 09:31:07 +08:00
Wyon Bi f8436d0541 video/drm: Add dsi driver for rk618
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Id8a7044352835fc4a6f733c6cf7a3d318f7f8c56
2020-08-13 09:30:51 +08:00
Wyon Bi ee93770137 video/drm: Add mode_set callback for bridge
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Id08455aacc850074b1bdb67776a4182598ccdb4f
2020-08-13 09:30:51 +08:00
Elaine Zhang 403d8d4c21 clk: rockchip: rk322x: add support to set and get spi clock
Change-Id: I361aa06aa795d2c041d2bdad9ee5ff6982d554fc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-13 09:29:49 +08:00
Elaine Zhang 7f619f26d7 clk: rockchip: rk3128: add support to set and get spi clock
Change-Id: I4ac874ba0542474baf18491f986f401c831a5ad4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-13 09:29:49 +08:00
Elaine Zhang df77e7a38c clk: rockchip: rk3036: add support to set and get spi clock
Change-Id: I24db5f250fa89845b62005950d520600434adb99
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-13 09:29:49 +08:00
Elaine Zhang db5be31cab clk: rockchip: rv1108: add support to set and get spi clock
Change-Id: I96891a4adb53bbb84e27cc0ac5eddf3c613c1baa
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2020-08-13 09:29:49 +08:00
Jon Lin 4243946213 mtd: mtd_blk: Implement mtd_dwrite none-alinged write
Change-Id: I605ee52083ef5d9d2863f347390acc635eabd2bc
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-08-13 09:29:03 +08:00
Jason Zhu 3fb7bf029a mtd: mtd_blk: implement mtd_dread_prepare()
Prepare to read data, then data is transmitted in background.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Iab560f7f903549a0b6c27f7e8e2ac984ae2ac75c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-08-13 09:29:03 +08:00
Jason Zhu 7863dac107 dm: mmc: remove mmc_bread_prepare in mmc_blk_ops
Merge it to mmc_bread() with using op_flag.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I3f63ebf66c43184a134c49a39a62feb2d5ae9821
2020-08-11 09:11:21 +08:00