The Rockchip DWC3 controller only support DRD mode (Dual Role
Device), but not support OTG mode. So if the dr_mode in DTS is
configured to OTG, then we force it to Host mode. This patch
does not affect the device function of OTG, such as rockusb.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I806623aa9b0bb8b595417755db7d9c6b6c4f38f1
In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.
Change-Id: Ib93da14b5309ec094b952e03f8514817910fedfa
Signed-off-by: William Wu <william.wu@rock-chips.com>
Add "fasboot getvar snapshot-update-status" support and
prevent erase/wipe of userdata/metadata when virtual A/B
merge status is MERGING or SNAPSHOTTED (+source slot !=
current slot).
Signed-off-by: Dayao Ji <jdy@rock-chips.com>
Change-Id: Ibb6ea5778b78b2601178f489d6efcee60d5d0a49
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Change-Id: I2f6f4d3598aaec1ed30ec3c3f8f594a675520203
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The EP Maxpacket should be varied due the USB speed may be changed
at enumeration time.
Change-Id: I6cf8e1e8b6e3c24d14f7b24638aff88f8dd066e0
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Change-Id: I2a546ac91632ea29d9ea88e94bfde948c387b834
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Use ofnode_ instead of fdt_ APIs so that the drivers can support live DT.
This patch updates usb_get_dr_mode() and usb_get_maximum_speed() to use
ofnode as parameter instead of fdt offset. And all the drivers who use
these APIs update to use live dt APIs at the same time.
Change-Id: I41a3fa52e8fdb99f7fc36b1bc0eb21ae82f90e63
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(am from http://patchwork.ozlabs.org/patch/1248682/)
Use dev_read_addr_ptr() instead of devfdt_get_addr() so that we can support
live DT.
Change-Id: I373931c2bfbe4ad4422ee974560e690c775d670d
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(am from http://patchwork.ozlabs.org/patch/1248684/)
The fdtdec.h is no use in this file, remove the include code.
Change-Id: I6e4e9dddae68ba4466eba7a22e8362840f048910
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(am from http://patchwork.ozlabs.org/patch/1248681/)
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.
Change-Id: I7fe45af396098749b2acf4a885dff875dcbc6f63
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.
Change-Id: Id90ac25a7e82bbf7918cc9658797c23008871852
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Change-Id: If8bffb5a8dc1b02e4b3100dc722d14a3d9b74992
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Through contrast test, the use of 256K buffer can improve the
download speed than 128K buffer about 14% for USB2 and 27% for USB3.
The statistics on RK3328-EVB as below:
Buffer USB2.0 USB3.0
128K 21MB/S 30MB/S
256K 24MB/S 38MB/S
Change-Id: I3b040ed225b212196fc5ca677a4fce240ad290f3
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
According to the chapter 8.2.3.3 of DWC3 Databook, the total size
of a Buffer Descriptor must be a multiple of MaxPacketSize for OUT
endpoints. This commit fixes it.
Change-Id: I7a4ae8ee73561c06cb4927cb83b4ae18a3f46c43
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
CSP bit of TRB Control is useful for protocols such CDC EEM/ECM/NCM
where we're transferring in blocks of MTU-sized requests (usually MTU
is 1500 bytes).
We know we will always have a short packet after two (for HS)
wMaxPacketSize packets and, usually, we will have a long(-ish) queue of
requests (for our g_ether gadget, we have at least 10 requests).
Instead of always stopping the queue processing to interrupt, giveback
and restart, let's tell dwc3 to interrupt but continue processing
following request if we have anything already pending in the queue.
Refer to commit ca4d44ea2a91 ("usb: dwc3: gadget: always enable CSP")
in Linux Kernel.
Change-Id: Icce79fa174f6d7f040e1c332fe6792a1922c5a04
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The DWC3 with Innosilicon USB 3.0 PHY on Rockchip platforms
(e.g. rk3328, rk1808) has problem to exit to U0 state from
U1 or U2 state when DWC3 work as peripheral mode. This patch
adds a quirk to reject transition to U1 and U2 state to
workaround this issue.
Refer to commit aaa5c055cc06 ("usb: dwc3: add dis-u1u2-quirk to
reject enter U1 and U2") in Rockchip Linux Kernel-4.4 .
Change-Id: I1f4176caab3ccdc31ba7eb06684267833bf804db
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface
initialization code would handle them properly along with UNKNOWN
type by default if none of the user/board doesn't need to use the
phy interfaces at all.
The current code is masking the 8/16-bit UTMI+ interface bits globally
which indeed effect the UNKNOWN cases, therefore it effects the platforms
which are not using phy interfaces at all.
So, handle the phy masking bits accordingly on respective interface
type cases.
Conflicts:
drivers/usb/dwc3/core.h
Change-Id: I28ce66d68984e30fa308a0b5a52c321d7bd96eda
Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot")
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 5c207282f53f86ecbf8c25cb691030d8c643ba1c)
Since, commit 62f9b6544728 ("common: Move older CPU functions to their own header")
cache ops functions are declared in a separate header. Include the same
to avoid build warnings.
Change-Id: I76b3f46ce7e8988335380a22038fb12296ccfb75
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit bdf30e84909d8d99c2700a0fc6c3e799e3d8e2d4)
U-Boot has two different variants of dwc3 initializations,
- with dm variant gadget, so the respective dm driver would
call the dwc3_init in core.
- with non-dm variant gadget, so the usage board file would
call dwc3_uboot_init in core.
The driver probe would handle all respective gadget properties
including phy interface via phy_type property and then trigger
dwc3_init for dm-variant gadgets.
So, to support the phy interface for non-dm variant gadgets,
the better option is dwc3_uboot_init since there is no
dedicated controller for non-dm variant gadgets.
This patch support for adding phy interface like 8/16-bit UTMI+
code for dwc3_uboot.
This change used Linux phy.h enum list, to make proper code
compatibility.
Conflicts:
drivers/usb/dwc3/core.h
Change-Id: I626e2428b548a2624fead5418ecb8f7571c77e89
Cc: Marek Vasut <marex@denx.de>
Tested-by: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 6b7ebff00190649d2136b34f6feebc0dbe85bfdc)
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"
Fix this by converting dwc2_fifo_read to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.
Change-Id: I2cc286df6fda386353cd2d350534e8ae398e67bb
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 7dc0ac6015718f5fb66bb79bf53df19f64fbfeee)
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"
Fix this by converting two functions to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.
Conflicts:
drivers/usb/gadget/composite.c
Change-Id: I9a42dcd3ca1a633204396e2a2699069a88df0890
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 616ebd8b9cb455c5949bd94c47283835eba1954a)
xhci.h has now been moved to include/usb/ directory. Therefore, update the
path in the Cadence USB drivers.
Change-Id: Id8eb19ff4ee0130265b14d9f350f6f78c6d691aa
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit e5521b1c6f4e2d18f7b33e6db06af5e47fdef52c)
The xHCI 1.1 version also need set Transfer Type field
Change-Id: Icd6c9f61352f56037566c356773a1908726897ab
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit e0891bb679200a8cc73c3b3d98ba40c02c31b850)
Add a new bcdDevice entry for Cadence USB gadget controller similar to
other controller and add gadget_is_cdns3() macro as well.
Conflicts:
drivers/usb/gadget/gadget_chips.h
Change-Id: I9be2baf3a8b57a0b1fb9116f51a04a71d59bb5f0
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit d80effb1847822e521cda17b4c73c83629b035d0)
Add driver to handle TI specific wrapper for Cadence USB3 controller
present on J721e SoC. Based on Linux driver for the same.
Change-Id: I68fb3c8144633bb6f363ee0f5dd7f5461d4a38a0
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit a9ca4193bd3d96f1545d30c4b6a6845442403f26)
Implement udc_set_speed() callback to limit Controller's speed to
high-speed/full-speed when working with gadgets that are high-speed or
full-speed only
Change-Id: Iee46beaf6336dc974597b3163287344c4bda2771
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 927c22b0dae7ee9e3e89d8be6393b030371cb842)
Add support for USB3 host and gadget driver. This is a direct sync of
Linux kernel Cadence USB stack that from v5.4-rc1 release.
Driver has been modified so that it compiles without errors against
U-Boot code base.
Features not required for U-Boot such as scatter-gather DMA and OTG
interrupt handling has been dropped.
Change-Id: I168e032f35d259ad1bb7a7f9f3c066bd13f129d4
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
[jjhiblot@ti.com: Add PHY support]
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 7e91f6ccdc84fe5952e5c26769e65d12e5fc4733)
This patch was copied from kernel commit: 67fdfda4a99ed.
Sometimes, the gadget driver we want to run has max_speed lower than
what the UDC supports. In such situations, UDC might want to make sure
we don't try to connect on speeds not supported by the gadget
driver because that will just fail.
So here introduce a new optional ->udc_set_speed() method which can be
implemented by interested UDC drivers to achieve this purpose.
Change-Id: I8ce57970c9095a92553ee12520e3724bd029d6b6
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 8d94e184ffdef48b40942c12d9e7b0290e60a1ef)
Add match_ep() op to usb_gadget_ops similar to Linux kernel which is
useful in finding a suitable ep match for the function driver. This will
avoid adding more gadget_is_xxx() handling code to usb_ep_autoconfig().
Also sync usb_ep_caps struct thats is usually used in the match_ep()
callback by the gadget controller driver
Change-Id: I94fe5d1b3ae984cbf3f6e10f86020191d8ca8090
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 77dcbdf3c1ce96de19c00caca0766b5bbaa0cf28)
Profiling the EHCI driver shows a significant performance problem in
ehci_submit_async(). Specifically, this function keeps enabling and
disabling async schedule back and forth for every single transaction.
However, enabling/disabling the async schedule does not take effect
immediatelly, but instead may take up to 1 mS (8 uFrames) to complete.
This impacts USB storage significantly, esp. since the recent reduction
of maximum transfer size to support more USB storage devices. This in
turn results in sharp increase in the number of ehci_submit_async()
calls. Since one USB storage BBB transfer does three such calls and
the maximum transfer size is 120 kiB, the overhead is 6 mS per 120 kiB,
which is unacceptable.
However, this overhead can be removed simply by keeping the async
schedule running. Specifically, the first transfer starts the async
schedule and then each and every subsequent transfer only adds a new
QH into that schedule, waits until the QH is completed and does NOT
disable the async schedule. The async schedule is stopped only by
shutting down the controller, which must happen before moving out
of U-Boot, otherwise the controller will corrupt memory.
Change-Id: I33a5eccac2579be09c5f1c9385ae245e680bc125
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 02b0e1a36c5bc20174299312556ec4e266872bd6)
Calling cache flush on invalid buffer, even with zero length might cause
an exception on certain platforms.
Change-Id: Idf8e2c87a24c80627279faa69430881d5c2c6800
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit fd15b58c1a9a61edcdeef8ce1eb4df2442295f58)
This is needed to make Windows THOR flash tool happy, because it
starts sending data only when interrupt packet is received on the 3rd
endpoint.
Change-Id: I51b9eee20646a7a0f65a1282fe96a575d3ebead7
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit ade08db8993687926773b32a477d9a24a9ede9e7)
Some boards don't populate clk/reset entries as these are are optional
as per binding documentation. Therefore, don't fail driver probe if
clk/reset entries are absent in DT.
This fixes fastboot failures seen due to enabling of CONFIG_CLK on AM57xx
Change-Id: I5a8e1d24f74b78647fd263ba11eaf68d4252abb5
Fixes: e8e683d33b0c ("board: ti: am57xx-idk: Configure the CDCE913 clock synthesizer")
Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit d624434f5ebc5e3eb5f5609f06200f477cf8d8b5)
The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
to work.
This patch only supports OTG0 with UTMI PHY.
Change-Id: Iccbcd113f87e5382eab12558abbb7ff596e4688d
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 235f5e158e336371759f98ffbf265fe078cda251)
This fixes the issues with calculation of controller indexes in
ehci_usb_bind() for iMX7, as USB controllers on iMX7 SoCs aren't
placed next to each other, and their addresses incremented by 0x10000.
Example of USB nodes for iMX7S/D:
usbotg1: usb@30b10000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b10000 0x200>;
^^^^^^^^^^
....
usbotg2: usb@30b20000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b20000 0x200>;
^^^^^^^^^^
....
usbh: usb@30b30000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b30000 0x200>;
^^^^^^^^^^
....
Which was leading to usb enumeration issues:
Colibri iMX7 # usb start
starting USB...
Bus usb@30b10000: USB EHCI 1.00
Bus usb@30b20000: probe failed, error -22
scanning bus usb@30b10000 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
Change-Id: I2c458dfa9e590ba054f63bb1e7ce1fad525eb56c
Fixes: 501547cec1("usb: ehci-mx6: Fix bus enumeration for DM case")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1198a104d37b10064cd90f36d472787d549eda02)
Add a new function that read quirk and configuration information from the
DT. The goal is to allow platforms using their own version of DWC3 driver
to migrate to the generic DWC3 driver.
The function is adapted from the function dwc3_get_properties() in the
linux dwc3 driver introduced in commit c5ac6116db35d.
Change-Id: I0716519c36b390cee532d3556e136012a277d036
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit ba6c5f7a28c8f8ac9eae194c2d37afa0ef51cb3d)
There is no need to fail if the maximum speed is not specified.
If the speed is not specified, do the same as linux and assume super speed.
Change-Id: I6fd5df9a3536a939b96915f6e260904da947e466
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1a63e5e5fbfff7779ce24b404bef3b8ccddf1a8b)
Currently the host driver used by dwc3-generic is "xhci-dwc3". This is
a functional driver but it doesn't use the dwc3 core and, in particular,
it lacks some bits that may be important.
For example on the k2 platforms, it is important that the phy are properly
suspended when the USB is not used anymore. The dwc3 core also has a
partial support for quirks.
The new driver can be used as a drop-in replacement for "xhci-dwc3".
In terms of implementation, it may seem strange that 2 private structures
dwc3_generic_host_priv and dwc3_generic_priv) are used. The reason for this
is simply that the xhci layer expects a struct xhci_ctrl at the beginning
of the private data and it seemed wasteful to include it also for the
peripheral case.
Change-Id: I68b9e506836292d5de24feb55c5619d907c173ef
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit b575e909168ca559609f6793720c4811b1dd55fd)
Factor code for re-usability.
This is another step toward adding host support.
Change-Id: I7c59c13bd9df4839e77555a45720fe318acde94c
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1af590df164f88fffb6484842eec8c8d8e500e70)
Separate platform data from the private data.
This is one step toward adding host support.
Change-Id: Ibd70d22283d064c77a179105c7e7f5675a598c49
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 3a38a0adb95bfebbbd39b2bb164f04bdeb10bc03)
No one is actually implementing those functions.
We could remove calls to these altogether, but it does not really hurt to
keep the empty inlined version at the moment and it satisfies a symmetry
with the gadget mode.
Change-Id: Icad0b0babdda6150088d722984b03d9cdf5c368b
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 33a99b43651b58fbb10f3778a16dd4c0a4db9708)
The xhci.h header file is currently located under drivers/usb/xhci
Move it to the include/usb folder to make it available to drivers that
are not under drivers/usb/xhci
Change-Id: I13705562893b30327708fbc321547bac79615785
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1708a12377b98397606677e117f93f07d7cd2f7e)
This allow the phy to enter idle and then suspend.
the K2 platforms require the PHY to be suspended before the USB domain
clock can be turned off.
Change-Id: Id674a95ff3cacb9e614cdc583f4a755e8301b7d7
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit bbe3d4a6c14e17d251029e4dde07f184244e9a4a)
This driver is not used anymore.
Conflicts:
configs/avnet_ultra96_rev1_defconfig
configs/xilinx_zynqmp_zcu100_revC_defconfig
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
configs/xilinx_zynqmp_zcu104_revA_defconfig
configs/xilinx_zynqmp_zcu104_revC_defconfig
configs/xilinx_zynqmp_zcu106_revA_defconfig
configs/xilinx_zynqmp_zcu111_revA_defconfig
drivers/usb/host/Kconfig
drivers/usb/host/xhci-zynqmp.c
Change-Id: I1faf3a98a74132ca2b2ba8b35931dee2c5bd5822
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit a8973731a452323e8767e8f9775c7d06921ebed5)
Phy setup should be done before dwc3 soft core reset as it is done
in linux & this fixes unreliable detection of usb cable on host side.
Change-Id: I4e49d99544d0cd4a6c4215652b9ca328d29ce24c
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 1a031d236a9eeb28ced5438242987ae6a45f3054)
Yifeng Zhao
William Wu
Jon Lin
Dayao Ji
Joseph Chen
Frank Wang
Kever Yang
Jagan Teki
Vignesh Raghavendra
Simon Goldschmidt
Chunfeng Yun
Sherry Sun
Marek Vasut
Marek Szyprowski
Ye Li
Igor Opaniuk
Jean-Jacques Hiblot
T Karthik Reddy