- disable virq chip by default;
- fix bank->use_count little than 0;
Change-Id: I69aa07cc2924dab40eea6524588869361ad8cf66
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Enable gpio irq only when child pin irq is request.
Change-Id: I429839c7dcdcb90cfe58738eeb36c7445fb0152b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
- using IRQ_X() to print message;
- update some comment;
- rename some function;
- add more strict irq sanity;
Change-Id: If5432818d4bc12fc1aa0b8aca6898bbf79dfa9fb
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
In the function gpio_get_intr_type, 'type' may be
used uninitialized if not add default process.
Change-Id: I917fecc2ed06cc844c30c93508084f32608edf6f
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
gic irq handler only need private data, while gpio irq(parent bank)
handler needs private data and irq number for getting gpio bank and
pin information. So we need deliver both of them to the irq handler.
This patch fixes the legacy code issue.
Change-Id: I1917b588a867e807cbd15e2e4101ae259cf4a40f
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This patch add support for IRQ interrupt, FIQ not included.
It will be enabled when you select CONFIG_GICV2 or CONFIG_GICV3.
The framework support gic interrupt and gpio interrupt, relative APIs
are provided in: ./include/irq-platform.h
If you'd like to add a new platform support into interrupt framework,
please follow the steps:
1. add relative definitions in the file like other platforms:
./include/irq-platform.h
2. add GICD, GICC and GICR(for GICV3) base address definitions in the
rkxxx-common.h, they are needed in: arch/arm/cpu/armv8/start.S;
3. enable CONFIG_GICV2 or CONFIG_GICV3.
Notice:
1. the framework is initialize in function 'interrupt_init()' of
_sequence_r[]. So you should not request irqs too early.
2. IRQ stack size is configured by CONFIG_IRQ_STACK_SIZE, the default
value is 8KB when CONFIG_IRQ_STACK_SIZE is absent.
Change-Id: I3d9e29873c9d64cd28aabd13a61111438c5902b0
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Joseph Chen
Jason Zhu