ARM: rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCY
Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the frequency of the ARM Generic Timer (aka. arch timer). ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same purpose. It seems useful to unify them. Since there are less occurences of the latter version, lets convert all users over to COUNTER_FREQUENCY. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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@ -188,11 +188,11 @@ ENTRY(_nonsec_init)
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* we do this here instead.
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* we do this here instead.
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* But first check if we have the generic timer.
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* But first check if we have the generic timer.
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*/
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*/
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#ifdef CONFIG_TIMER_CLK_FREQ
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#ifdef COUNTER_FREQUENCY
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mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
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mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
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and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
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and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
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cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
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cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
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ldreq r1, =CONFIG_TIMER_CLK_FREQ
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ldreq r1, =COUNTER_FREQUENCY
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mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
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mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
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#endif
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#endif
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@ -46,7 +46,7 @@ static u32 __secure cp15_read_cntp_ctl(void)
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return val;
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return val;
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}
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}
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#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000)
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#define ONE_MS (COUNTER_FREQUENCY / 1000)
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static void __secure __mdelay(u32 ms)
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static void __secure __mdelay(u32 ms)
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{
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{
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@ -100,14 +100,14 @@ int board_init(void)
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* we avoid the risk of writing to it.
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* we avoid the risk of writing to it.
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*/
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*/
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
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if (freq != CONFIG_TIMER_CLK_FREQ) {
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if (freq != COUNTER_FREQUENCY) {
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debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
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debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
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freq, CONFIG_TIMER_CLK_FREQ);
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freq, COUNTER_FREQUENCY);
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#ifdef CONFIG_NON_SECURE
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#ifdef CONFIG_NON_SECURE
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printf("arch timer frequency is wrong, but cannot adjust it\n");
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printf("arch timer frequency is wrong, but cannot adjust it\n");
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#else
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#else
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asm volatile("mcr p15, 0, %0, c14, c0, 0"
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asm volatile("mcr p15, 0, %0, c14, c0, 0"
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: : "r"(CONFIG_TIMER_CLK_FREQ));
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: : "r"(COUNTER_FREQUENCY));
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#endif
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#endif
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}
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}
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}
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}
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@ -23,7 +23,7 @@
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/* input clock of PLL: 24MHz input clock */
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/* input clock of PLL: 24MHz input clock */
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#define CONFIG_SYS_CLK_FREQ 24000000
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#define CONFIG_SYS_CLK_FREQ 24000000
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#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_CMDLINE_TAG
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@ -243,7 +243,7 @@
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CONFIG_TIMER_CLK_FREQ 12500000
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#define COUNTER_FREQUENCY 12500000
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#define CONFIG_HWCONFIG
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 256
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#define HWCONFIG_BUFFER_SIZE 256
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@ -500,7 +500,7 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CONFIG_TIMER_CLK_FREQ 12500000
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#define COUNTER_FREQUENCY 12500000
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#define CONFIG_HWCONFIG
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 256
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#define HWCONFIG_BUFFER_SIZE 256
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@ -370,7 +370,7 @@
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CONFIG_TIMER_CLK_FREQ 12500000
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#define COUNTER_FREQUENCY 12500000
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#define CONFIG_HWCONFIG
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 256
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#define HWCONFIG_BUFFER_SIZE 256
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@ -21,7 +21,7 @@
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#define CONFIG_MXC_GPT_HCLK
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#define CONFIG_MXC_GPT_HCLK
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#define CONFIG_SYSCOUNTER_TIMER
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#define CONFIG_SYSCOUNTER_TIMER
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#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
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#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
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#define CONFIG_TIMER_CLK_FREQ CONFIG_SC_TIMER_CLK
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#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SYS_BOOTM_LEN 0x1000000
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#define CONFIG_SYS_BOOTM_LEN 0x1000000
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@ -18,7 +18,6 @@
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#define CONFIG_SUNXI_USB_PHYS 1
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#define CONFIG_SUNXI_USB_PHYS 1
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#define COUNTER_FREQUENCY CONFIG_TIMER_CLK_FREQ
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#define GICD_BASE 0x1c81000
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#define GICD_BASE 0x1c81000
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#define GICC_BASE 0x1c82000
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#define GICC_BASE 0x1c82000
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@ -46,7 +46,7 @@
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#endif
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#endif
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/* CPU */
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/* CPU */
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#define CONFIG_TIMER_CLK_FREQ 24000000
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#define COUNTER_FREQUENCY 24000000
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/*
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/*
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* The DRAM Base differs between some models. We cannot use macros for the
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* The DRAM Base differs between some models. We cannot use macros for the
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@ -6453,7 +6453,6 @@ CONFIG_TI816X_EVM_DDR3
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CONFIG_TI816X_USE_EMIF0
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CONFIG_TI816X_USE_EMIF0
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CONFIG_TI816X_USE_EMIF1
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CONFIG_TI816X_USE_EMIF1
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CONFIG_TI81XX
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CONFIG_TI81XX
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CONFIG_TIMER_CLK_FREQ
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CONFIG_TIMESTAMP
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CONFIG_TIMESTAMP
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CONFIG_TIZEN
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CONFIG_TIZEN
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CONFIG_TI_KEYSTONE_SERDES
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CONFIG_TI_KEYSTONE_SERDES
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