video/drm: analogix_dp: add edp reset control support
This patch adds eDP software reset operation to make sure register access successfully on RK3288 and it fixes possible register default value abnormal issue during boot up. 1) normal case: Rockchip UBOOT DRM driver version: v1.0.1 0x120: 0x00000007 0x390: 0x00000003 Using display timing dts Detailed mode clock 200000 kHz, flags[a] H: 1536 1548 1564 1612 V: 2048 2056 2060 2068 bus_format: 100e Link Training success! final link rate = 0x06, lane count = 0x04 2) abnormal case: Rockchip UBOOT DRM driver version: v1.0.1 0x120: 0x00000066 0x390: 0x00000202 Using display timing dts Detailed mode clock 200000 kHz, flags[a] H: 1536 1548 1564 1612 V: 2048 2056 2060 2068 bus_format: 100e failed to get Rx Max Link Rate failed to init training unable to do link train Change-Id: Idacbb0c72a40442da3a87e60bfe1d9965f3ca79c Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
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@ -828,6 +828,11 @@ static int analogix_dp_connector_init(struct display_state *state)
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break;
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}
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/* eDP software reset request */
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reset_assert(&dp->reset);
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udelay(1);
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reset_deassert(&dp->reset);
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analogix_dp_init_dp(dp);
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return 0;
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@ -917,6 +922,12 @@ static int analogix_dp_probe(struct udevice *dev)
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if (IS_ERR(dp->grf))
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return PTR_ERR(dp->grf);
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ret = reset_get_by_name(dev, "dp", &dp->reset);
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if (ret) {
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dev_err(dev, "failed to get reset control: %d\n", ret);
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return ret;
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}
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ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio,
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GPIOD_IS_IN);
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if (ret && ret != -ENOENT) {
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@ -7,6 +7,8 @@
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#ifndef __DRM_ANALOGIX_DP_H__
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#define __DRM_ANALOGIX_DP_H__
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#include <reset.h>
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/*
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* Unless otherwise noted, all values are from the DP 1.1a spec. Note that
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* DP and DPCD versions are independent. Differences from 1.0 are not noted,
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@ -1071,6 +1073,7 @@ struct analogix_dp_device {
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struct udevice *dev;
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void *reg_base;
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void *grf;
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struct reset_ctl reset;
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struct gpio_desc hpd_gpio;
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struct video_info video_info;
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struct link_train link_train;
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