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rockchip: rk3399: use common board file 

Use common board file and move SoC spec setting into rk3399.c

Change-Id: Ic674cef566b16c33978a1430eadfa9438b2de1db
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2018-01-22 14:44:10 +08:00
parent 9814e89b69
commit db48fc9697
4 changed files with 80 additions and 266 deletions
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183
arch/arm/mach-rockchip/rk3399-board-spl.c
View File

@ -1,183 +0,0 @@
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/bootrom.h>
#include <asm/arch/clock.h>
#include <asm/arch/grf_rk3399.h>
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <asm/io.h>
#include <debug_uart.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <ram.h>
#include <spl.h>
#include <syscon.h>
DECLARE_GLOBAL_DATA_PTR;
void board_return_to_bootrom(void)
{
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
}
static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
[BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
};
const char *board_spl_was_booted_from(void)
{
u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR);
const char *bootdevice_ofpath = NULL;
if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
bootdevice_ofpath = boot_devices[bootdevice_brom_id];
if (bootdevice_ofpath)
debug("%s: brom_bootdevice_id %x maps to '%s'\n",
__func__, bootdevice_brom_id, bootdevice_ofpath);
else
debug("%s: failed to resolve brom_bootdevice_id %x\n",
__func__, bootdevice_brom_id);
return bootdevice_ofpath;
}
u32 spl_boot_device(void)
{
u32 boot_device = BOOT_DEVICE_MMC1;
if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
return BOOT_DEVICE_BOOTROM;
return boot_device;
}
u32 spl_boot_mode(const u32 boot_device)
{
return MMCSD_MODE_RAW;
}
#define TIMER_CHN10_BASE 0xff8680a0
#define TIMER_END_COUNT_L 0x00
#define TIMER_END_COUNT_H 0x04
#define TIMER_INIT_COUNT_L 0x10
#define TIMER_INIT_COUNT_H 0x14
#define TIMER_CONTROL_REG 0x1c
#define TIMER_EN 0x1
#define TIMER_FMODE (0 << 1)
#define TIMER_RMODE (1 << 1)
void secure_timer_init(void)
{
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
}
void board_debug_uart_init(void)
{
#define GRF_BASE 0xff770000
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
/* Enable early UART0 on the RK3399 */
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C0_SEL_MASK,
GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C1_SEL_MASK,
GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
#else
/* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C4_SEL_MASK,
GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
/* Set channel C as UART2 input */
rk_clrsetreg(&grf->soc_con7,
GRF_UART_DBG_SEL_MASK,
GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
#endif
}
void board_init_f(ulong dummy)
{
struct udevice *pinctrl;
struct udevice *dev;
struct rk3399_pmusgrf_regs *sgrf;
struct rk3399_grf_regs *grf;
int ret;
#define EARLY_UART
#ifdef EARLY_UART
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
printascii("U-Boot SPL board init");
#endif
secure_timer_init();
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
/*
* Disable DDR and SRAM security regions.
*
* As we are entered from the BootROM, the region from
* 0x0 through 0xfffff (i.e. the first MB of memory) will
* be protected. This will cause issues with the DW_MMC
* driver, which tries to DMA from/to the stack (likely)
* located in this range.
*/
sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
/* eMMC clock generator: disable the clock multipilier */
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrreg(&grf->emmccore_con[11], 0x0ff);
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("Pinctrl init failed: %d\n", ret);
return;
}
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
return;
}
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif

113
arch/arm/mach-rockchip/rk3399/rk3399.c
View File

@ -5,13 +5,12 @@
*/ */
#include <common.h> #include <common.h>
#include <syscon.h>
#include <asm/armv8/mmu.h> #include <asm/armv8/mmu.h>
#include <asm/arch/boot_mode.h> #include <asm/arch/bootrom.h>
#include <asm/arch/clock.h>
#include <asm/arch/grf_rk3399.h> #include <asm/arch/grf_rk3399.h>
#include <asm/arch/hardware.h> #include <asm/arch/hardware.h>
#include <asm/io.h> #include <asm/io.h>
#include <syscon.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -40,47 +39,91 @@ static struct mm_region rk3399_mem_map[] = {
struct mm_region *mem_map = rk3399_mem_map; struct mm_region *mem_map = rk3399_mem_map;
int dram_init_banksize(void) const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
[BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
};
#ifdef CONFIG_SPL_BUILD
#define TIMER_CHN10_BASE 0xff8680a0
#define TIMER_END_COUNT_L 0x00
#define TIMER_END_COUNT_H 0x04
#define TIMER_INIT_COUNT_L 0x10
#define TIMER_INIT_COUNT_H 0x14
#define TIMER_CONTROL_REG 0x1c
#define TIMER_EN 0x1
#define TIMER_FMODE (0 << 1)
#define TIMER_RMODE (1 << 1)
void rockchip_stimer_init(void)
{ {
size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
/* Reserve 0x200000 for ATF bl31 */ writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
gd->bd->bi_dram[0].start = 0x200000; writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
printf("%s\n", __func__);
return 0;
} }
#define GRF_BASE 0xff770000
#define PMUGRF_BASE 0xff320000
#define PMUSGRF_BASE 0xff330000
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
/* We do some SoC one time setting here. */ struct rk3399_pmusgrf_regs *sgrf = (void *)PMUSGRF_BASE;
struct rk3399_pmugrf_regs *pmugrf = (void *)PMUGRF_BASE;
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
/* Emmc clock generator: disable the clock multipilier */ /* We do some SoC one time setting here. */
rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); /*
* Disable DDR and SRAM security regions.
*
* As we are entered from the BootROM, the region from
* 0x0 through 0xfffff (i.e. the first MB of memory) will
* be protected. This will cause issues with the DW_MMC
* driver, which tries to DMA from/to the stack (likely)
* located in this range.
*/
rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
/* eMMC clock generator: disable the clock multipilier */
rk_clrreg(&grf->emmccore_con[11], 0x0ff);
/* PWM3 select pwm3a io */ /* PWM3 select pwm3a io */
rk_clrreg(PMU_GRF_SOC_CON0, 1 << 5); rk_clrreg(&pmugrf->soc_con0, 1 << 5);
return 0;
}
int board_late_init(void)
{
setup_boot_mode();
return 0;
}
#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
int fb_set_reboot_flag(void)
{
struct rk3399_pmugrf_regs *pmugrf;
printf("Setting reboot to fastboot flag ...\n");
pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
/* Clear boot mode */
writel(BOOT_FASTBOOT, &pmugrf->os_reg0);
return 0; return 0;
} }
#endif #endif
void board_debug_uart_init(void)
{
#define GRF_BASE 0xff770000
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
/* Enable early UART0 on the RK3399 */
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C0_SEL_MASK,
GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C1_SEL_MASK,
GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
#else
/* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C4_SEL_MASK,
GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
/* Set channel C as UART2 input */
rk_clrsetreg(&grf->soc_con7,
GRF_UART_DBG_SEL_MASK,
GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
#endif
}

33
board/rockchip/evb_rk3399/evb-rk3399.c
View File

@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define RK3399_CPUID_OFF 0x7 #define RK3399_CPUID_OFF 0x7
#define RK3399_CPUID_LEN 0x10 #define RK3399_CPUID_LEN 0x10
int board_init(void) int rk_board_init(void)
{ {
struct udevice *pinctrl, *regulator; struct udevice *pinctrl, *regulator;
int ret; int ret;
@ -58,10 +58,6 @@ int board_init(void)
goto out; goto out;
} }
ret = regulators_enable_boot_on(false);
if (ret)
debug("%s: Cannot enable boot on regulator\n", __func__);
ret = regulator_get_by_platname("vcc5v0_host", &regulator); ret = regulator_get_by_platname("vcc5v0_host", &regulator);
if (ret) { if (ret) {
debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
@ -211,30 +207,3 @@ int board_usb_init(int index, enum usb_init_type init)
return dwc3_uboot_init(&dwc3_device_data); return dwc3_uboot_init(&dwc3_device_data);
} }
#endif #endif
void spl_board_init(void)
{
struct udevice *pinctrl;
int ret;
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("%s: Cannot find pinctrl device\n", __func__);
goto err;
}
/* Enable debug UART */
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
if (ret) {
debug("%s: Failed to set up console UART\n", __func__);
goto err;
}
preloader_console_init();
return;
err:
printf("%s: Error %d\n", __func__, ret);
/* No way to report error here */
hang();
}

17
board/theobroma-systems/puma_rk3399/puma-rk3399.c
View File

@ -25,21 +25,6 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
int ret;
/*
* We need to call into regulators_enable_boot_on() again, as the call
* during SPL may have not included all regulators.
*/
ret = regulators_enable_boot_on(false);
if (ret)
debug("%s: Cannot enable boot on regulator\n", __func__);
return 0;
}
static void rk3399_force_power_on_reset(void) static void rk3399_force_power_on_reset(void)
{ {
ofnode node; ofnode node;
@ -62,7 +47,7 @@ static void rk3399_force_power_on_reset(void)
dm_gpio_set_value(&sysreset_gpio, 1); dm_gpio_set_value(&sysreset_gpio, 1);
} }
void spl_board_init(void) void rk_spl_board_init(void)
{ {
int ret; int ret;
struct rk3399_cru *cru = rockchip_get_cru(); struct rk3399_cru *cru = rockchip_get_cru();