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crypto: rockchip: v1: make input buffer CONFIG_SYS_CACHELINE_SIZE aligned 

Avoid warning from flush_dcache(): "CACHE: Misaligned operation at range ..."

Change-Id: I8879a3a0dc324463dc5e042bace183a6a2d453a5
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
This commit is contained in:
Lin Jinhan 2019-12-02 17:23:45 +08:00 committed by Joseph Chen
parent b5038b6202
commit da2d9dd013
1 changed files with 5 additions and 1 deletions
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6
drivers/crypto/rockchip/crypto_v1.c
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@ -96,6 +96,7 @@ static int rockchip_crypto_sha_update(struct udevice *dev,
{ {
struct rockchip_crypto_priv *priv = dev_get_priv(dev); struct rockchip_crypto_priv *priv = dev_get_priv(dev);
struct rk_crypto_reg *reg = priv->reg; struct rk_crypto_reg *reg = priv->reg;
ulong aligned_input, aligned_len;
if (!len) if (!len)
return -EINVAL; return -EINVAL;
@ -103,7 +104,10 @@ static int rockchip_crypto_sha_update(struct udevice *dev,
priv->length += len; priv->length += len;
/* Must flush dcache before crypto DMA fetch data region */ /* Must flush dcache before crypto DMA fetch data region */
flush_cache((unsigned long)input, len); aligned_input = round_down((ulong)input, CONFIG_SYS_CACHELINE_SIZE);
aligned_len = round_up(len + ((ulong)input - aligned_input),
CONFIG_SYS_CACHELINE_SIZE);
flush_cache(aligned_input, aligned_len);
/* Wait last complete */ /* Wait last complete */
do {} while (readl(&reg->crypto_ctrl) & HASH_START); do {} while (readl(&reg->crypto_ctrl) & HASH_START);