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mmc: sdhci: rockchip: reset the clock phase 

Reset the clock phase when the frequency is lower than 52MHz.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I49c50779ab5e1103d815cd2be1a7c9603cea397a
This commit is contained in:
Jason Zhu 2020-12-06 16:16:23 +08:00 committed by Jianhong Chen
parent 3c70338210
commit d62fa58224
1 changed files with 8 additions and 0 deletions
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8
drivers/mmc/rockchip_sdhci.c
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@ -347,6 +347,14 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo
extra = DWCMSHC_EMMC_DLL_DLYENA |
DLL_STRBIN_TAPNUM_DEFAULT;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
udelay(1);
} else {
/* reset the clock phase when the frequency is lower than 52MHz */
extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
udelay(1);
}
return ret;