From d62fa5822469b1dfaebec34f787b36192535024d Mon Sep 17 00:00:00 2001 From: Jason Zhu Date: Sun, 6 Dec 2020 16:16:23 +0800 Subject: [PATCH] mmc: sdhci: rockchip: reset the clock phase Reset the clock phase when the frequency is lower than 52MHz. Signed-off-by: Jason Zhu Change-Id: I49c50779ab5e1103d815cd2be1a7c9603cea397a --- drivers/mmc/rockchip_sdhci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 6cb9d246e7..56105702b4 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -347,6 +347,14 @@ static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clo extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_STRBIN_TAPNUM_DEFAULT; sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); + udelay(1); + } else { + /* reset the clock phase when the frequency is lower than 52MHz */ + extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; + sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); + udelay(1); } return ret;