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rv1126: ddr: wrlvl support dqs longger than clk 

Change-Id: I3c94787e1ffdc9f43c591b05002f0b70ffedf1ec
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
This commit is contained in:
Tang Yun ping 2020-06-22 10:03:12 +08:00 committed by Jianhong Chen
parent df8389e3dc
commit d5bb9a92b1
1 changed files with 5 additions and 3 deletions
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8
drivers/ram/rockchip/sdram_rv1126.c
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@ -117,7 +117,7 @@ static struct rv1126_fsp_param fsp_param[MAX_IDX];
static u8 lp3_odt_value; static u8 lp3_odt_value;
static u8 wrlvl_result[2][4]; static s8 wrlvl_result[2][4];
/* DDR configuration 0-9 */ /* DDR configuration 0-9 */
u16 ddr_cfg_2_rbc[] = { u16 ddr_cfg_2_rbc[] = {
@ -1858,7 +1858,9 @@ static int get_wrlvl_val(struct dram_info *dram,
lp_stat = low_power_update(dram, 0); lp_stat = low_power_update(dram, 0);
clk_skew = readl(PHY_REG(phy_base, 0x150 + 0x17)); clk_skew = 0x1f;
modify_ca_deskew(dram, DESKEW_MDF_ABS_VAL, clk_skew, clk_skew, 3,
sdram_params->base.dramtype);
ret = data_training(dram, 0, sdram_params, 0, WRITE_LEVELING); ret = data_training(dram, 0, sdram_params, 0, WRITE_LEVELING);
if (sdram_params->ch.cap_info.rank == 2) if (sdram_params->ch.cap_info.rank == 2)
@ -1884,7 +1886,7 @@ static int high_freq_training(struct dram_info *dram,
void __iomem *phy_base = dram->phy; void __iomem *phy_base = dram->phy;
u32 dramtype = sdram_params->base.dramtype; u32 dramtype = sdram_params->base.dramtype;
int min_val; int min_val;
u32 dqs_skew, clk_skew, ca_skew; int dqs_skew, clk_skew, ca_skew;
int ret; int ret;
dqs_skew = 0; dqs_skew = 0;