UPSTREAM: mtd: cfi: Add support for status register polling
The status register is optional in the AMD command sets, but it's presence can be checked by reading out CFI table entry 0xc bit 0. If the register is present, prefer using it's bit 7 to determine if the flash is busy over reading the flash ; this is needed ie. on Hyperflash memories. Change-Id: If82e42e5320123ef0cf5b436e4f6f0d68393f2b3 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> (cherry picked from commit 72443c7f7d2174903e73ee88dcb4364e0387bbb2)
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@ -544,7 +544,16 @@ static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
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#ifdef CONFIG_FLASH_CFI_LEGACY
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case CFI_CMDSET_AMD_LEGACY:
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#endif
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retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
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if (info->sr_supported) {
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flash_write_cmd (info, sect, info->addr_unlock1,
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FLASH_CMD_READ_STATUS);
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retval = !flash_isset (info, sect, 0,
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FLASH_STATUS_DONE);
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} else {
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retval = flash_toggle (info, sect, 0,
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AMD_STATUS_TOGGLE);
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}
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break;
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default:
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retval = 0;
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@ -1685,6 +1694,7 @@ static void cmdset_amd_read_jedec_ids(flash_info_t *info)
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{
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ushort bankId = 0;
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uchar manuId;
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uchar lsbits;
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flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
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flash_unlock_seq(info, 0);
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@ -1700,6 +1710,9 @@ static void cmdset_amd_read_jedec_ids(flash_info_t *info)
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}
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info->manufacturer_id = manuId;
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lsbits = flash_read_uchar(info, FLASH_OFFSET_LOWER_SW_BITS);
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info->sr_supported = lsbits & BIT(0);
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switch (info->chipwidth){
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case FLASH_CFI_8BIT:
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info->device_id = flash_read_uchar (info,
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@ -42,6 +42,7 @@ typedef struct {
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ushort cfi_offset; /* offset for cfi query */
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ulong addr_unlock1; /* unlock address 1 for AMD flash roms */
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ulong addr_unlock2; /* unlock address 2 for AMD flash roms */
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uchar sr_supported; /* status register supported */
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const char *name; /* human-readable name */
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#endif
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#ifdef CONFIG_MTD
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@ -62,6 +62,7 @@
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#define FLASH_OFFSET_MANUFACTURER_ID 0x00
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#define FLASH_OFFSET_DEVICE_ID 0x01
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#define FLASH_OFFSET_LOWER_SW_BITS 0x0C
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#define FLASH_OFFSET_DEVICE_ID2 0x0E
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#define FLASH_OFFSET_DEVICE_ID3 0x0F
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#define FLASH_OFFSET_CFI 0x55
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