mmc: rework ddr mode judgement with timing

Since the card device is set the proper timing after speed mode switch
is completed, host driver can get ddr_mode from timing parameter. So
drop the antiquated ddr_mode.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>

cmd/mmc.c

@@ -38,7 +38,7 @@ static void print_mmcinfo(struct mmc *mmc)
 	print_size(mmc->capacity, "\n");
 
 	printf("Bus Width: %d-bit%s\n", mmc->bus_width,
-			mmc->ddr_mode ? " DDR" : "");
+			mmc_card_ddr(mmc) ? " DDR" : "");
 
 	puts("Erase Group Size: ");
 	print_size(((u64)mmc->erase_grp_size) << 9, "\n");

drivers/mmc/dw_mmc.c

@@ -432,7 +432,7 @@ static int dwmci_set_ios(struct mmc *mmc)
 	dwmci_writel(host, DWMCI_CTYPE, ctype);
 
 	regs = dwmci_readl(host, DWMCI_UHS_REG);
-	if (mmc->ddr_mode)
+	if (mmc_card_ddr(mmc))
 		regs |= DWMCI_DDR_MODE;
 	else
 		regs &= ~DWMCI_DDR_MODE;

drivers/mmc/fsl_esdhc.c

@@ -407,7 +407,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 #if defined(CONFIG_FSL_USDHC)
 	esdhc_write32(&regs->mixctrl,
 	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
-			| (mmc->ddr_mode ? XFERTYP_DDREN : 0));
+			| (mmc_card_ddr(mmc) ? XFERTYP_DDREN : 0));
 	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
 #else
 	esdhc_write32(&regs->xfertyp, xfertyp);
@@ -548,7 +548,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
 	while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
 		div++;
 
-	pre_div >>= 1;
+	pre_div >>= mmc_card_ddr(mmc) ? 2 : 1;
 	div -= 1;
 
 	clk = (pre_div << 8) | (div << 4);

drivers/mmc/mmc.c

@@ -210,7 +210,7 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
 {
 	struct mmc_cmd cmd;
 
-	if (mmc->ddr_mode)
+	if (mmc_card_ddr(mmc))
 		return 0;
 
 	cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
@@ -1933,7 +1933,6 @@ int mmc_start_init(struct mmc *mmc)
 	if (err)
 		return err;
 #endif
-	mmc->ddr_mode = 0;
 	mmc_set_bus_width(mmc, 1);
 	mmc_set_clock(mmc, 1);
 	mmc_set_timing(mmc, MMC_TIMING_LEGACY);

drivers/mmc/uniphier-sd.c

@@ -532,7 +532,7 @@ static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
 	u32 tmp;
 
 	tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE);
-	if (mmc->ddr_mode)
+	if (mmc_card_ddr(mmc))
 		tmp |= UNIPHIER_SD_IF_MODE_DDR;
 	else
 		tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
@@ -599,7 +599,7 @@ static int uniphier_sd_set_ios(struct udevice *dev)
 	int ret;
 
 	dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
-		mmc->clock, mmc->ddr_mode, mmc->bus_width);
+		mmc->clock, mmc_card_ddr(mmc), mmc->bus_width);
 
 	ret = uniphier_sd_set_bus_width(priv, mmc);
 	if (ret)

drivers/mmc/xenon_sdhci.c

@@ -237,7 +237,7 @@ static void xenon_mmc_phy_set(struct sdhci_host *host)
 	sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
 
 	var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);
-	if (host->mmc->ddr_mode) {
+	if (mmc_card_ddr(host->mmc)) {
 		var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
 	} else {
 		var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |
@@ -329,7 +329,7 @@ static void xenon_sdhci_set_ios_post(struct sdhci_host *host)
 	if (IS_SD(host->mmc)) {
 		/* SD/SDIO */
 		if (pwr_18v) {
-			if (host->mmc->ddr_mode)
+			if (mmc_card_ddr(host->mmc))
 				priv->timing = MMC_TIMING_UHS_DDR50;
 			else if (speed <= 25000000)
 				priv->timing = MMC_TIMING_UHS_SDR25;
@@ -343,7 +343,7 @@ static void xenon_sdhci_set_ios_post(struct sdhci_host *host)
 		}
 	} else {
 		/* eMMC */
-		if (host->mmc->ddr_mode)
+		if (mmc_card_ddr(host->mmc))
 			priv->timing = MMC_TIMING_MMC_DDR52;
 		else if (speed <= 26000000)
 			priv->timing = MMC_TIMING_LEGACY;

include/mmc.h

@@ -527,7 +527,6 @@ struct mmc {
 	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
 	char init_in_progress;	/* 1 if we have done mmc_start_init() */
 	char preinit;		/* start init as early as possible */
-	int ddr_mode;
 #if CONFIG_IS_ENABLED(DM_MMC)
 	struct udevice *dev;	/* Device for this MMC controller */
 #endif