UPSTREAM: configs: Move CONFIG_SPI_FLASH into defconfigs

Completely move CONFIG_SPI_FLASH from remaining board header files to
defconfigs

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Change-Id: Iab125975d8e45a953666dcc04c989da9ae9b7f93
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ea4805d6b26282451eee9c701a456225bcf7db85)
This commit is contained in:
Vignesh R 2019-02-05 11:29:10 +05:30 committed by Kever Yang
parent a1e428c28f
commit c964ade639
36 changed files with 35 additions and 10 deletions

View File

@ -51,6 +51,10 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y

View File

@ -52,6 +52,7 @@ CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y

View File

@ -54,6 +54,7 @@ CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y

View File

@ -53,6 +53,7 @@ CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y

View File

@ -62,6 +62,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_REGULATOR_FIXED=y

View File

@ -26,6 +26,7 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_PHY=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y

View File

@ -50,6 +50,7 @@ CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

View File

@ -55,6 +55,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_KEY=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

View File

@ -52,6 +52,7 @@ CONFIG_DM_KEY=y
CONFIG_ADC_KEY=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

View File

@ -47,6 +47,7 @@ CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

View File

@ -56,6 +56,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_REGULATOR_FIXED=y

View File

@ -28,6 +28,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y

View File

@ -29,6 +29,7 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y

View File

@ -40,6 +40,7 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y

View File

@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y

View File

@ -37,6 +37,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y

View File

@ -50,6 +50,7 @@ CONFIG_DM_KEY=y
CONFIG_ADC_KEY=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

View File

@ -50,6 +50,7 @@ CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

View File

@ -47,6 +47,7 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

View File

@ -75,6 +75,7 @@ CONFIG_ADC_KEY=y
CONFIG_LED=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_REGULATOR_FIXED=y

View File

@ -84,6 +84,7 @@ CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

View File

@ -65,6 +65,7 @@ CONFIG_GPIO_KEY=y
CONFIG_RK_KEY=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_FUEL_GAUGE=y

View File

@ -80,6 +80,7 @@ CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y

View File

@ -45,6 +45,7 @@ CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

View File

@ -40,6 +40,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set

View File

@ -49,6 +49,7 @@ CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y

View File

@ -33,7 +33,8 @@ CONFIG_MISC=y
CONFIG_ATSHA204A=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_PHYLIB=y
CONFIG_SPI_FLASH=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000

View File

@ -42,6 +42,10 @@ CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y

View File

@ -35,7 +35,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
/* SPI NOR */
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI

View File

@ -292,8 +292,6 @@ unsigned long get_board_ddr_clk(void);
/* SPI */
#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
#define CONFIG_SPI_FLASH
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST

View File

@ -37,7 +37,6 @@
#define SDRAM_BANK_SIZE (512UL << 20UL)
#define SDRAM_MAX_SIZE 0x80000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI
#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SF_DEFAULT_SPEED 20000000

View File

@ -42,7 +42,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_MAX_SIZE 0x80000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000

View File

@ -48,7 +48,6 @@
#define SDRAM_BANK_SIZE (2UL << 30)
#define SDRAM_MAX_SIZE 0x80000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000

View File

@ -49,7 +49,6 @@
#define SDRAM_BANK_SIZE (2UL << 30)
#define SDRAM_MAX_SIZE 0xfe000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000

View File

@ -46,7 +46,6 @@
#define CONFIG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000

View File

@ -42,7 +42,6 @@
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
/*