UPSTREAM: configs: Move CONFIG_SPI_FLASH into defconfigs
Completely move CONFIG_SPI_FLASH from remaining board header files to defconfigs Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed Change-Id: Iab125975d8e45a953666dcc04c989da9ae9b7f93 Signed-off-by: Jon Lin <jon.lin@rock-chips.com> (cherry picked from commit ea4805d6b26282451eee9c701a456225bcf7db85)
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@ -51,6 +51,10 @@ CONFIG_CMD_FS_GENERIC=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_SF=y
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CONFIG_USB_FUNCTION_FASTBOOT=y
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CONFIG_FASTBOOT_BUF_ADDR=0x12000000
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CONFIG_FSL_ESDHC=y
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CONFIG_SPI_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_USB=y
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CONFIG_USB_STORAGE=y
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@ -52,6 +52,7 @@ CONFIG_CROS_EC_SPI=y
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CONFIG_PWRSEQ=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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@ -54,6 +54,7 @@ CONFIG_CROS_EC_SPI=y
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CONFIG_PWRSEQ=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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@ -53,6 +53,7 @@ CONFIG_CROS_EC_SPI=y
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CONFIG_PWRSEQ=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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@ -62,6 +62,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_LED=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_REGULATOR_FIXED=y
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@ -26,6 +26,7 @@ CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_PHY=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PINCTRL=y
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@ -50,6 +50,7 @@ CONFIG_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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@ -55,6 +55,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_DM_KEY=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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@ -52,6 +52,7 @@ CONFIG_DM_KEY=y
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CONFIG_ADC_KEY=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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@ -47,6 +47,7 @@ CONFIG_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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@ -56,6 +56,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_LED=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_REGULATOR_FIXED=y
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@ -28,6 +28,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_PHY_GIGE=y
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@ -29,6 +29,7 @@ CONFIG_DM=y
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CONFIG_FSL_CAAM=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_PHY_GIGE=y
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@ -40,6 +40,7 @@ CONFIG_DM=y
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CONFIG_FSL_CAAM=y
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CONFIG_NAND=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_PHY_GIGE=y
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@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_FSL_CAAM=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_PHY_GIGE=y
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@ -37,6 +37,7 @@ CONFIG_ENV_IS_IN_MMC=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_PHYLIB=y
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CONFIG_NETDEVICES=y
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CONFIG_PHY_GIGE=y
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@ -50,6 +50,7 @@ CONFIG_DM_KEY=y
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CONFIG_ADC_KEY=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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@ -50,6 +50,7 @@ CONFIG_MISC=y
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CONFIG_I2C_EEPROM=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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@ -47,6 +47,7 @@ CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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@ -75,6 +75,7 @@ CONFIG_ADC_KEY=y
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CONFIG_LED=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_REGULATOR_FIXED=y
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@ -84,6 +84,7 @@ CONFIG_MISC=y
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CONFIG_ROCKCHIP_EFUSE=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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@ -65,6 +65,7 @@ CONFIG_GPIO_KEY=y
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CONFIG_RK_KEY=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_FUEL_GAUGE=y
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@ -80,6 +80,7 @@ CONFIG_MISC=y
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CONFIG_ROCKCHIP_EFUSE=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PINCTRL=y
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CONFIG_DM_PMIC=y
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@ -45,6 +45,7 @@ CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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@ -40,6 +40,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_LED=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_PINCTRL=y
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CONFIG_DM_PMIC=y
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# CONFIG_SPL_PMIC_CHILDREN is not set
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@ -49,6 +49,7 @@ CONFIG_MISC=y
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CONFIG_I2C_EEPROM=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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@ -33,7 +33,8 @@ CONFIG_MISC=y
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CONFIG_ATSHA204A=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_MV=y
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CONFIG_PHYLIB=y
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CONFIG_SPI_FLASH=y
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CONFIG_PHY_MARVELL=y
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CONFIG_PHY_GIGE=y
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CONFIG_DEBUG_UART_BASE=0xd0012000
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CONFIG_DEBUG_UART_CLOCK=250000000
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@ -42,6 +42,10 @@ CONFIG_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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@ -35,7 +35,6 @@
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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/* SPI NOR */
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_SST
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#define CONFIG_MXC_SPI
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@ -292,8 +292,6 @@ unsigned long get_board_ddr_clk(void);
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/* SPI */
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#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
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#define CONFIG_SPI_FLASH
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#ifdef CONFIG_FSL_DSPI
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_SST
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@ -37,7 +37,6 @@
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#define SDRAM_BANK_SIZE (512UL << 20UL)
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#define SDRAM_MAX_SIZE 0x80000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SPI_FLASH_GIGADEVICE
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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@ -42,7 +42,6 @@
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#define CONFIG_SYS_SDRAM_BASE 0x60000000
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#define SDRAM_MAX_SIZE 0x80000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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@ -48,7 +48,6 @@
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#define SDRAM_BANK_SIZE (2UL << 30)
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#define SDRAM_MAX_SIZE 0x80000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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@ -49,7 +49,6 @@
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#define SDRAM_BANK_SIZE (2UL << 30)
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#define SDRAM_MAX_SIZE 0xfe000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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@ -46,7 +46,6 @@
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#define CONFIG_SYS_SDRAM_BASE 0
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#define SDRAM_MAX_SIZE 0xff000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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@ -42,7 +42,6 @@
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/* SPI NOR flash default params, used by sf commands */
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#define CONFIG_SF_DEFAULT_SPEED 1000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_SPANSION
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/*
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