diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
index 0c59adad02..03fc221408 100644
--- a/arch/arm/dts/rk3128.dtsi
+++ b/arch/arm/dts/rk3128.dtsi
@@ -301,6 +301,18 @@
 		#dma-cells = <2>;
 	};
 
+	saradc: saradc@2006c000 {
+		compatible = "rockchip,saradc";
+		reg = <0x2006c000 0x100>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		#io-channel-cells = <1>;
+		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
+		status = "disabled";
+	};
+
 	pwm0: pwm0@20050000 {
 		compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 		reg = <0x20050000 0x10>;
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
index 36c8006bd2..35e943575f 100644
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -29,6 +29,7 @@
 #define SCLK_TIMER1		86
 #define SCLK_TIMER2		87
 #define SCLK_TIMER3		88
+#define SCLK_SARADC		91
 #define SCLK_OTGPHY0		93
 #define SCLK_LCDC		100
 #define SCLK_HDMI		109
@@ -58,6 +59,7 @@
 #define ACLK_PERI		210
 
 /* pclk gates */
+#define PCLK_SARADC		318
 #define PCLK_GPIO0		320
 #define PCLK_GPIO1		321
 #define PCLK_GPIO2		322
@@ -160,6 +162,7 @@
 #define SRST_EMMC		83
 #define SRST_SPI0		84
 #define SRST_WDT		86
+#define SRST_SARADC		87
 #define SRST_DDRPHY		88
 #define SRST_DDRPHY_P		89
 #define SRST_DDRCTRL		90