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rockchip: dts: rk3128: Add SARADC at dtsi level 

Change-Id: Ifcbda377d5b0eff50bd41cfc6141eb1f76211dc2
Signed-off-by: David Wu <david.wu@rock-chips.com>
This commit is contained in:
David Wu 2017-10-16 14:42:05 +08:00 committed by Kever Yang
parent f3d84b4a51
commit c95ecb1990
2 changed files with 15 additions and 0 deletions
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12
arch/arm/dts/rk3128.dtsi
View File

@ -301,6 +301,18 @@
#dma-cells = <2>;
};
saradc: saradc@2006c000 {
compatible = "rockchip,saradc";
reg = <0x2006c000 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};
pwm0: pwm0@20050000 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050000 0x10>;

3
include/dt-bindings/clock/rk3128-cru.h
View File

@ -29,6 +29,7 @@
#define SCLK_TIMER1 86
#define SCLK_TIMER2 87
#define SCLK_TIMER3 88
#define SCLK_SARADC 91
#define SCLK_OTGPHY0 93
#define SCLK_LCDC 100
#define SCLK_HDMI 109
@ -58,6 +59,7 @@
#define ACLK_PERI 210
/* pclk gates */
#define PCLK_SARADC 318
#define PCLK_GPIO0 320
#define PCLK_GPIO1 321
#define PCLK_GPIO2 322
@ -160,6 +162,7 @@
#define SRST_EMMC 83
#define SRST_SPI0 84
#define SRST_WDT 86
#define SRST_SARADC 87
#define SRST_DDRPHY 88
#define SRST_DDRPHY_P 89
#define SRST_DDRCTRL 90