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irq: gicv3: Enables Group 1 interrupts for the current Security state 

When a CPU enters a low power state, the registers ICC_IGRPEN1_EL1 is lost.
It need to re-initialise.

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I62d9eed2b29190134d95ebd153f21aa764c4ab3b
This commit is contained in:
shengfei Xu 2020-05-19 10:47:38 +08:00 committed by Jianhong Chen
parent b4e0791886
commit c2bb46e4a5
1 changed files with 5 additions and 0 deletions
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5
drivers/irq/irq-gic.c
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@ -320,6 +320,11 @@ static int gic_irq_resume(void)
gicd_writel(gicd_save.ctlr, GICD_CTLR); gicd_writel(gicd_save.ctlr, GICD_CTLR);
dsb(); dsb();
#if defined(CONFIG_GICV3)
asm volatile("msr " __stringify(ICC_IGRPEN1_EL1) ", %0" : : "r" (1));
dsb();
#endif
return 0; return 0;
} }