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pwm: rockchip: Do pwm pinctrl setting after pwm enabled 

If the PWM pinctrl uses default state, the iomux setting will
be done at probe, the PWM may not be enabled at this moment.
It will make PWM into an intermediate state, destroy the default
hardware state, the PWM is not ready for work yet. So it is better
for doing PWM pinctrl setting after PWM enabled.

Change-Id: I8b700a07083b9a6798303fc5a5ed9f29eb42c47e
Signed-off-by: David Wu <david.wu@rock-chips.com>
This commit is contained in:
David Wu 2018-03-16 16:47:08 +08:00 committed by Kever Yang
parent fdd40e0026
commit bab0c55c3c
9 changed files with 35 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/dts/rk3036.dtsi
View File

@ -152,7 +152,7 @@
compatible = "rockchip,rk2928-pwm";
reg = <0x20050000 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@ -163,7 +163,7 @@
compatible = "rockchip,rk2928-pwm";
reg = <0x20050010 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@ -174,7 +174,7 @@
compatible = "rockchip,rk2928-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@ -185,7 +185,7 @@
compatible = "rockchip,rk2928-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";

8
arch/arm/dts/rk3066a.dtsi
View File

@ -637,22 +637,22 @@
};
&pwm0 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_out>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_out>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_out>;
};
&pwm3 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_out>;
};

8
arch/arm/dts/rk3128.dtsi
View File

@ -312,7 +312,7 @@
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050000 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@ -322,7 +322,7 @@
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050010 0x10>;
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@ -332,7 +332,7 @@
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@ -342,7 +342,7 @@
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";

8
arch/arm/dts/rk3188.dtsi
View File

@ -551,22 +551,22 @@
};
&pwm0 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_out>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_out>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_out>;
};
&pwm3 {
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_out>;
};

8
arch/arm/dts/rk322x.dtsi
View File

@ -288,7 +288,7 @@
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
};
@ -299,7 +299,7 @@
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
};
@ -310,7 +310,7 @@
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
};
@ -321,7 +321,7 @@
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
};

8
arch/arm/dts/rk3288.dtsi
View File

@ -520,7 +520,7 @@
compatible = "rockchip,rk3288-pwm";
reg = <0xff680000 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@ -532,7 +532,7 @@
compatible = "rockchip,rk3288-pwm";
reg = <0xff680010 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@ -544,7 +544,7 @@
compatible = "rockchip,rk3288-pwm";
reg = <0xff680020 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
@ -556,7 +556,7 @@
compatible = "rockchip,rk3288-pwm";
reg = <0xff680030 0x10>;
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";

6
arch/arm/dts/rk3368.dtsi
View File

@ -592,7 +592,7 @@
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM1>;
clock-names = "pwm";
@ -603,7 +603,7 @@
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM1>;
clock-names = "pwm";
@ -623,7 +623,7 @@
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680030 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM1>;
clock-names = "pwm";

8
arch/arm/dts/rk3399.dtsi
View File

@ -1091,7 +1091,7 @@
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm0_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
@ -1102,7 +1102,7 @@
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm1_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
@ -1113,7 +1113,7 @@
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
@ -1124,7 +1124,7 @@
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420030 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-names = "active";
pinctrl-0 = <&pwm3a_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";

4
drivers/pwm/rk_pwm.c
View File

@ -9,6 +9,7 @@
#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <pwm.h>
#include <regmap.h>
#include <syscon.h>
@ -128,6 +129,9 @@ static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
if (priv->data->vop_pwm)
priv->vop_pwm_en = enable;
if (enable)
pinctrl_select_state(dev, "active");
return 0;
}