rockchip: rk3288: move configure_l2ctlr back to rk3288
The configure_l2ctlr() is used only by rk3288, do not need to locate in sys_proto.h Change-Id: I98f8cffdbc990e3fcf19f41ca53ff5fd25155e63 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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@ -7,27 +7,5 @@
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#ifndef _ASM_ARCH_SYS_PROTO_H
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#define _ASM_ARCH_SYS_PROTO_H
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#ifdef CONFIG_ROCKCHIP_RK3288
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#include <asm/armv7.h>
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static void configure_l2ctlr(void)
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{
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uint32_t l2ctlr;
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l2ctlr = read_l2ctlr();
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l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
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/*
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* Data RAM write latency: 2 cycles
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* Data RAM read latency: 2 cycles
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* Data RAM setup latency: 1 cycle
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* Tag RAM write latency: 1 cycle
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* Tag RAM read latency: 1 cycle
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* Tag RAM setup latency: 1 cycle
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*/
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l2ctlr |= (1 << 3 | 1 << 0);
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write_l2ctlr(l2ctlr);
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}
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#endif /* CONFIG_ROCKCHIP_RK3288 */
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#endif /* _ASM_ARCH_SYS_PROTO_H */
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@ -3,6 +3,7 @@
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/armv7.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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@ -20,10 +21,33 @@
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#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
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((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
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#ifdef CONFIG_SPL_BUILD
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static void configure_l2ctlr(void)
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{
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uint32_t l2ctlr;
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l2ctlr = read_l2ctlr();
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l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
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/*
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* Data RAM write latency: 2 cycles
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* Data RAM read latency: 2 cycles
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* Data RAM setup latency: 1 cycle
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* Tag RAM write latency: 1 cycle
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* Tag RAM read latency: 1 cycle
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* Tag RAM setup latency: 1 cycle
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*/
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l2ctlr |= (1 << 3 | 1 << 0);
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write_l2ctlr(l2ctlr);
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}
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#endif
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int arch_cpu_init(void)
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{
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/* We do some SoC one time setting here. */
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#ifdef CONFIG_SPL_BUILD
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configure_l2ctlr();
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#else
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/* Use rkpwm by default */
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rk_setreg(GRF_SOC_CON2, 1 << 0);
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@ -40,6 +64,7 @@ int arch_cpu_init(void)
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/* Set vop qos to highest priority */
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writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2), VIO0_VOP_QOS_BASE);
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writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2), VIO1_VOP_QOS_BASE);
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#endif
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return 0;
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}
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