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rockchip: clock: rk3399: support 400KHZ output for emmc initialization. 

support 400KHz output for emmc initialization

Change-Id: I4f2182981f587688c777f64c30d0eeb59f69b0ea
Signed-off-by: chenfen <chenfen@rock-chips.com>
This commit is contained in:
chenfen 2018-07-31 17:59:43 +08:00
parent 850fcf3e04
commit b2a78faeb5
1 changed files with 15 additions and 7 deletions
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22
drivers/clk/rockchip/clk_rk3399.c
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@ -758,7 +758,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
div = 2;
break;
case SCLK_EMMC:
con = readl(&cru->clksel_con[21]);
con = readl(&cru->clksel_con[22]);
div = 1;
break;
default:
@ -813,12 +813,20 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
/* Select clk_emmc source from GPLL too */
src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
assert(src_clk_div - 1 < 128);
rk_clrsetreg(&cru->clksel_con[22],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
(src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
if (src_clk_div > 128) {
/* use 24MHz source for 400KHz clock */
src_clk_div = DIV_ROUND_UP(OSC_HZ, set_rate);
assert(src_clk_div - 1 < 128);
rk_clrsetreg(&cru->clksel_con[22],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
(src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
} else {
rk_clrsetreg(&cru->clksel_con[22],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
(src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
}
break;
default:
return -EINVAL;