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UPSTREAM: rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASK 

The PLL selector field for NANDC is only 2 bits wide.
This fixes an 'int-overflow on shift' warning.

Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Change-Id: I4d6d7c51633eb7cd0fbfb1c6b7c501cf8c0fcf81
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit cd401abcd532c59cdaaf6ffeed762386c1813e58)
This commit is contained in:
Philipp Tomsich 2017-12-02 00:14:55 +01:00 committed by Kever Yang
parent 8ebcf66b48
commit b10789f201
1 changed files with 1 additions and 1 deletions
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2
arch/arm/include/asm/arch-rockchip/cru_rk3128.h
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@ -137,7 +137,7 @@ enum {
/* CRU_CLK_SEL2_CON */
NANDC_PLL_SEL_SHIFT = 14,
NANDC_PLL_SEL_MASK = 7 << NANDC_PLL_SEL_SHIFT,
NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT,
NANDC_PLL_SEL_CPLL = 0,
NANDC_PLL_SEL_GPLL,
NANDC_CLK_DIV_SHIFT = 8,