rockchip: px30: switch VCCIO6 voltage controlled by io_vsel6
According to the description of GRF_IO_VSEL, the voltage of VCCIO6(which is the concern of emmc/flash/sfc controller) will indicate by GPIO0_B6 or io_vsel6. The SOC defaults use GPIO0_B6 to indicate power supply voltage for VCCIO6 by hardware, then we can switch to io_vsel6 after system power on, and release GPIO0_B6 for other usage. Change-Id: I9c8339e357a7328d9ffeb711ba5d0bdd41971101 Signed-off-by: Liang Chen <cl@rock-chips.com>
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@ -142,6 +142,52 @@ enum {
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GPIO3A1_GPIO = 0,
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GPIO3A1_UART5_RX = 4,
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};
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enum {
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IOVSEL6_CTRL_SHIFT = 0,
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IOVSEL6_CTRL_MASK = BIT(0),
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VCCIO6_SEL_BY_GPIO = 0,
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VCCIO6_SEL_BY_IOVSEL6,
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IOVSEL6_SHIFT = 1,
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IOVSEL6_MASK = BIT(1),
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VCCIO6_3V3 = 0,
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VCCIO6_1V8,
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};
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/*
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* The voltage of VCCIO6(which is the voltage domain of emmc/flash/sfc
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* interface) can indicated by GPIO0_B6 or io_vsel6. The SOC defaults
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* use GPIO0_B6 to indicate power supply voltage for VCCIO6 by hardware,
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* then we can switch to io_vsel6 after system power on, and release GPIO0_B6
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* for other usage.
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*/
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#define GPIO0_B6 14
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#define GPIO0_BASE 0xff040000
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#define GPIO_SWPORTA_DDR 0x4
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#define GPIO_EXT_PORTA 0x50
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static int grf_vccio6_vsel_init(void)
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{
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static struct px30_grf * const grf = (void *)GRF_BASE;
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u32 val;
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val = readl(GPIO0_BASE + GPIO_SWPORTA_DDR);
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val &= ~BIT(GPIO0_B6);
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writel(val, GPIO0_BASE + GPIO_SWPORTA_DDR);
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if (readl(GPIO0_BASE + GPIO_EXT_PORTA) & BIT(GPIO0_B6))
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val = VCCIO6_SEL_BY_IOVSEL6 << IOVSEL6_CTRL_SHIFT |
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VCCIO6_1V8 << IOVSEL6_SHIFT;
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else
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val = VCCIO6_SEL_BY_IOVSEL6 << IOVSEL6_CTRL_SHIFT |
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VCCIO6_3V3 << IOVSEL6_SHIFT;
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rk_clrsetreg(&grf->io_vsel, IOVSEL6_CTRL_MASK | IOVSEL6_MASK, val);
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return 0;
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}
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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@ -185,6 +231,8 @@ int arch_cpu_init(void)
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/* Clear the force_jtag */
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rk_clrreg(GRF_CPU_CON1, 1 << 7);
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grf_vccio6_vsel_init();
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return 0;
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}
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