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rockchip: px5 update dts for spl/tpl 

TPL need dmc to init ddr sdram, and emmc, boot-order.

Change-Id: Ia783e1a47a7710bf618c556eefaf354b7097eacd
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2019-01-30 18:08:08 +08:00
parent d74e8763bb
commit a739a3a9b7
1 changed files with 29 additions and 0 deletions
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29
arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
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@ -3,6 +3,27 @@
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/ {
chosen {
u-boot,spl-boot-order = &emmc;
};
};
&dmc {
u-boot,dm-pre-reloc;
/*
* PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
* See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
* details on the 'rockchip,memory-schedule' property and how it
* affects the physical-address to device-address mapping.
*/
rockchip,memory-schedule = <DMC_MSCH_CBRD>;
rockchip,ddr-frequency = <800000000>;
rockchip,ddr-speed-bin = <DDR3_1600K>;
status = "okay";
};
&pinctrl {
u-boot,dm-pre-reloc;
@ -21,6 +42,10 @@
u-boot,dm-pre-reloc;
};
&sgrf {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
@ -32,3 +57,7 @@
&uart4 {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};