rkflash: add nand_mega_area description
Change-Id: Ibf4ab2b6d7d4d0e58f859ee47ec52c3cced79238 Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
Jianhong Chen
parent
c3a9bbca4b
commit
a6fcac41dc
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@ -16,76 +16,84 @@
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static struct nand_info spi_nand_tbl[] = {
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/* TC58CVG0S0HxAIx */
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{0x98C2, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 18, 8, 0xFF, 0xFF, 4, 8, NULL},
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{0x98C2, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 18, 8, 0xFF, 0xFF, {4, 8, 0xff, 0xff}, NULL},
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/* TC58CVG1S0HxAIx */
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{0x98CB, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 19, 8, 0xFF, 0xFF, 4, 8, NULL},
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{0x98CB, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 19, 8, 0xFF, 0xFF, {4, 8, 0xff, 0xff}, NULL},
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/* MX35LF1GE4AB */
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{0xC212, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1},
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{0xC212, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0, {4, 8, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* MX35LF2GE4AB */
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{0xC222, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1},
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{0xC222, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0, {4, 8, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* GD5F1GQ4UAYIG */
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{0xC8F1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, NULL},
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{0xC8F1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, {4, 8, 0xff, 0xff}, NULL},
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/* MT29F1G01ZAC */
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{0x2C12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1},
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{0x2C12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xB0, 0, {4, 8, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* GD5F2GQ40BY2GR */
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{0xC8D2, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3},
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/* GD5F1GQ4U */
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{0xC8D1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3},
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{0xC8D2, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0, {4, 8, 0xff, 0xff}, &sfc_nand_ecc_status_sp3},
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/* GD5F1GQ4RB9IGR */
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{0xC8D1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, {4, 8, 0xff, 0xff}, &sfc_nand_ecc_status_sp3},
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/* IS37SML01G1 */
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{0xC821, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xFF, 0xFF, 8, 12, &sfc_nand_ecc_status_sp1},
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{0xC821, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xFF, 0xFF, {8, 12, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* W25N01GV */
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{0xEFAA, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 4, 20, &sfc_nand_ecc_status_sp1},
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{0xEFAA, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, {4, 20, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* HYF2GQ4UAACAE */
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{0xC952, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL},
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{0xC952, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, {4, 36, 0xff, 0xff}, NULL},
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/* HYF2GQ4UDACAE */
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{0xC922, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, NULL},
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{0xC922, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, {4, 20, 0xff, 0xff}, NULL},
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/* HYF2GQ4UHCCAE */
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{0xC95A, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL},
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{0xC95A, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, {4, 36, 0xff, 0xff}, NULL},
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/* HYF1GQ4UDACAE */
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{0xC921, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, NULL},
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{0xC921, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, {4, 20, 0xff, 0xff}, NULL},
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/* F50L1G41LB */
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{0xC801, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 20, 36, &sfc_nand_ecc_status_sp1},
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{0xC801, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, {20, 36, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* XT26G02A */
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{0x0BE2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4},
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{0x0BE2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, {8, 12, 0xff, 0xff}, &sfc_nand_ecc_status_sp4},
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/* XT26G01A */
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{0x0BE1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4},
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{0x0BE1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, {8, 12, 0xff, 0xff}, &sfc_nand_ecc_status_sp4},
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/* FS35ND01G-S1 */
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{0xCDB1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 16, 20, &sfc_nand_ecc_status_sp5},
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{0xCDB1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, {16, 20, 0xff, 0xff}, &sfc_nand_ecc_status_sp5},
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/* FS35ND02G-S2 */
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{0xCDA2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x03, 0x02, 0xD8, 0x00, 19, 4, 0xFF, 0xFF, 16, 20, &sfc_nand_ecc_status_sp5},
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{0xCDA2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x03, 0x02, 0xD8, 0x00, 19, 4, 0xFF, 0xFF, {16, 20, 0xff, 0xff}, &sfc_nand_ecc_status_sp5},
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/* DS35Q1GA-1B */
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{0xE571, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1},
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{0xE571, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, {4, 20, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* DS35Q2GA-1B */
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{0xE572, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1},
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{0xE572, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0x0, {4, 20, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* EM73C044SNC-G */
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{0xD522, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0x0, 4, 20, NULL},
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{0xD522, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0x0, {4, 20, 0xff, 0xff}, NULL},
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/* EM73D044SNB-G */
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{0xD520, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0x0, 4, 20, NULL},
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{0xD520, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0x0, {4, 20, 0xff, 0xff}, NULL},
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/* ATO25D1GA */
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{0x9B12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x40, 18, 1, 0xB0, 0x0, 20, 36, &sfc_nand_ecc_status_sp1},
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{0x9B12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x40, 18, 1, 0xB0, 0x0, {20, 36, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* XT26G02B */
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{0x0BF2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4},
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{0x0BF2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, {8, 12, 0xff, 0xff}, &sfc_nand_ecc_status_sp5},
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/* XT26G01B */
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{0x0BF1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4},
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{0x0BF1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, {8, 12, 0xff, 0xff}, &sfc_nand_ecc_status_sp4},
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/* HYF4GQ4UAACBE */
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{0xC9D4, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 4, 0xB0, 0, 32, 64, NULL},
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{0xC9D4, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 4, 0xB0, 0, {32, 64, 36, 68}, NULL},
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/* FM25S01 */
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{0xA1A1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0, 0, 4, &sfc_nand_ecc_status_sp1},
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{0xA1A1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0, {0, 4, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* HYF1GQ4UPACAE */
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{0xC9A1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, &sfc_nand_ecc_status_sp1},
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{0xC9A1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, {4, 20, 0xff, 0xff}, &sfc_nand_ecc_status_sp1},
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/* EM73E044SNA-G */
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{0xD503, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 8, 0xB0, 0, 4, 40, NULL},
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{0xD503, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 8, 0xB0, 0, {4, 40, 8, 44}, NULL},
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/* GD5F2GQ5UEYIG */
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{0xC852, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, &sfc_nand_ecc_status_sp2},
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{0xC852, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, {4, 20, 0xff, 0xff}, &sfc_nand_ecc_status_sp2},
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/* GD5F1GQ4R */
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{0xC8C1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3},
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{0xC8C1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, {4, 8, 0xff, 0xff}, &sfc_nand_ecc_status_sp3},
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/* TC58CVG2S0HRAIJ */
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{0x98ED, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 20, 8, 0xFF, 0xFF, {4, 12, 8, 16}, NULL},
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/* TC58CVG1S3HRAIJ */
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{0x98EB, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xFF, 0xFF, {4, 8, 0xff, 0xff}, NULL},
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/* TC58CVG0S3HRAIJ */
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{0x98E2, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xFF, 0xFF, {4, 8, 0xff, 0xff}, NULL},
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/* XT26G04A */
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{0x0BE3, 4, 128, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 1, 0xB0, 0x0, {8, 12, 0xff, 0xff}, &sfc_nand_ecc_status_sp4},
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};
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static struct nand_info *p_nand_info;
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static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4];
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static struct SFNAND_DEV sfc_nand_dev;
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static struct nand_info *spi_nand_get_info(u8 *nand_id)
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static struct nand_info *sfc_nand_get_info(u8 *nand_id)
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{
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u32 i;
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u32 id = (nand_id[0] << 8) | (nand_id[1] << 0);
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@ -182,6 +190,7 @@ static int sfc_nand_wait_busy(u8 *data, int timeout)
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/*
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* ecc default:
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* ecc bits: 0xC0[4,5]
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* 0x00, No bit errors were detected
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* 0x01, Bit errors were detected and corrected.
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* 0x10, Multiple bit errors were detected and not corrected.
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@ -219,6 +228,7 @@ static u32 sfc_nand_ecc_status(void)
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/*
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* ecc spectial type1:
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* ecc bits: 0xC0[4,5]
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* 0x00, No bit errors were detected;
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* 0x01, Bits errors were detected and corrected, bit error count
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* may reach the bit flip detection threshold;
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@ -256,6 +266,7 @@ u32 sfc_nand_ecc_status_sp1(void)
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/*
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* ecc spectial type2:
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* ecc bits: 0xC0[4,5] 0xF0[4,5]
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* [0x0000, 0x0011], No bit errors were detected;
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* [0x0100, 0x0111], Bit errors were detected and corrected. Not
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* reach Flipping Bits;
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@ -297,13 +308,14 @@ u32 sfc_nand_ecc_status_sp2(void)
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/*
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* ecc spectial type3:
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* ecc bits: 0xC0[4,5] 0xF0[4,5]
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* [0x0000, 0x0011], No bit errors were detected;
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* [0x0100, 0x0111], Bit errors were detected and corrected. Not
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* reach Flipping Bits;
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* [0x1000, 0x1011], Multiple bit errors were detected and
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* not corrected.
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* [0x1100, 0x1111], Bit error count equals the bit flip
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* detectionthreshold
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* detectio nthreshold
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*/
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u32 sfc_nand_ecc_status_sp3(void)
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{
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@ -339,6 +351,7 @@ u32 sfc_nand_ecc_status_sp3(void)
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/*
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* ecc spectial type4:
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* ecc bits: 0xC0[2,5]
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* [0x0000], No bit errors were detected;
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* [0x0001, 0x0111], Bit errors were detected and corrected. Not
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* reach Flipping Bits;
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@ -378,6 +391,7 @@ u32 sfc_nand_ecc_status_sp4(void)
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/*
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* ecc spectial type5:
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* ecc bits: 0xC0[4,6]
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* [0x0], No bit errors were detected;
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* [0x001, 0x011], Bit errors were detected and corrected. Not
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* reach Flipping Bits;
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@ -425,6 +439,7 @@ u32 sfc_nand_erase_block(u8 cs, u32 addr)
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sfcmd.d32 = 0;
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sfcmd.b.cmd = p_nand_info->block_erase_cmd;
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sfcmd.b.addrbits = SFC_ADDR_24BITS;
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sfcmd.b.rw = SFC_WRITE;
|
||||
sfc_nand_write_en();
|
||||
ret = sfc_request(sfcmd.d32, 0, addr, NULL);
|
||||
if (ret != SFC_OK)
|
||||
|
|
@ -484,16 +499,15 @@ u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare)
|
|||
int ret;
|
||||
u32 sec_per_page = p_nand_info->sec_per_page;
|
||||
u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE;
|
||||
u32 spare_offs_1 = p_nand_info->spare_offs_1;
|
||||
u32 spare_offs_2 = p_nand_info->spare_offs_2;
|
||||
struct nand_mega_area *meta = &p_nand_info->meta;
|
||||
|
||||
memcpy(gp_page_buf, p_data, data_size);
|
||||
memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16);
|
||||
gp_page_buf[(data_size + spare_offs_1) / 4] = p_spare[0];
|
||||
gp_page_buf[(data_size + spare_offs_2) / 4] = p_spare[1];
|
||||
gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0];
|
||||
gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1];
|
||||
if (sec_per_page == 8) {
|
||||
gp_page_buf[(data_size + spare_offs_1) / 4 + 1] = p_spare[2];
|
||||
gp_page_buf[(data_size + spare_offs_2) / 4 + 1] = p_spare[3];
|
||||
gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2];
|
||||
gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3];
|
||||
}
|
||||
ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf);
|
||||
|
||||
|
|
@ -508,23 +522,25 @@ static u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf)
|
|||
union SFCCTRL_DATA sfctrl;
|
||||
u32 ecc_result;
|
||||
u32 sec_per_page = p_nand_info->sec_per_page;
|
||||
u8 status;
|
||||
|
||||
sfcmd.d32 = 0;
|
||||
sfcmd.b.cmd = p_nand_info->page_read_cmd;
|
||||
sfcmd.b.datasize = 0;
|
||||
sfcmd.b.rw = SFC_WRITE;
|
||||
sfcmd.b.addrbits = SFC_ADDR_24BITS;
|
||||
sfc_request(sfcmd.d32, 0, addr, p_page_buf);
|
||||
|
||||
if (p_nand_info->ecc_status)
|
||||
ecc_result = p_nand_info->ecc_status();
|
||||
else
|
||||
ecc_result = sfc_nand_ecc_status();
|
||||
|
||||
if (sfc_nand_dev.read_lines == DATA_LINES_X4 &&
|
||||
p_nand_info->feature & FEA_SOFT_QOP_BIT &&
|
||||
sfc_get_version() < SFC_VER_3)
|
||||
sfc_nand_rw_preset();
|
||||
|
||||
sfc_nand_wait_busy(&status, 1000 * 1000);
|
||||
if (p_nand_info->ecc_status)
|
||||
ecc_result = p_nand_info->ecc_status();
|
||||
else
|
||||
ecc_result = sfc_nand_ecc_status();
|
||||
|
||||
sfcmd.d32 = 0;
|
||||
sfcmd.b.cmd = sfc_nand_dev.page_read_cmd;
|
||||
sfcmd.b.datasize = SFC_NAND_SECTOR_FULL_SIZE * sec_per_page;
|
||||
|
|
@ -537,7 +553,7 @@ static u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf)
|
|||
rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]);
|
||||
|
||||
if (ret != SFC_OK)
|
||||
return SFC_NAND_HW_ERROR;
|
||||
return SFC_NAND_ECC_ERROR;
|
||||
|
||||
return ecc_result;
|
||||
}
|
||||
|
|
@ -547,16 +563,15 @@ u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare)
|
|||
int ret;
|
||||
u32 sec_per_page = p_nand_info->sec_per_page;
|
||||
u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE;
|
||||
u32 spare_offs_1 = p_nand_info->spare_offs_1;
|
||||
u32 spare_offs_2 = p_nand_info->spare_offs_2;
|
||||
struct nand_mega_area *meta = &p_nand_info->meta;
|
||||
|
||||
ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf);
|
||||
memcpy(p_data, gp_page_buf, data_size);
|
||||
p_spare[0] = gp_page_buf[(data_size + spare_offs_1) / 4];
|
||||
p_spare[1] = gp_page_buf[(data_size + spare_offs_2) / 4];
|
||||
p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4];
|
||||
p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4];
|
||||
if (p_nand_info->sec_per_page == 8) {
|
||||
p_spare[2] = gp_page_buf[(data_size + spare_offs_1) / 4 + 1];
|
||||
p_spare[3] = gp_page_buf[(data_size + spare_offs_2) / 4 + 1];
|
||||
p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4];
|
||||
p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4];
|
||||
}
|
||||
|
||||
if (ret != SFC_NAND_ECC_OK) {
|
||||
|
|
@ -576,7 +591,7 @@ u32 sfc_nand_check_bad_block(u8 cs, u32 addr)
|
|||
u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE;
|
||||
|
||||
ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf);
|
||||
if (ret)
|
||||
if (ret == SFC_NAND_ECC_ERROR)
|
||||
return true;
|
||||
/* Original bad block */
|
||||
if ((gp_page_buf[data_size / 4] & 0xFF) != 0xFF)
|
||||
|
|
@ -683,7 +698,7 @@ void sfc_nand_ftl_ops_init(void)
|
|||
g_nand_ops.bch_sel = NULL;
|
||||
}
|
||||
|
||||
static int spi_nand_enable_QE(void)
|
||||
static int sfc_nand_enable_QE(void)
|
||||
{
|
||||
int ret = SFC_OK;
|
||||
u8 status;
|
||||
|
|
@ -715,7 +730,7 @@ u32 sfc_nand_init(void)
|
|||
if (id_byte[0] == 0xFF || id_byte[0] == 0x00)
|
||||
return FTL_NO_FLASH;
|
||||
|
||||
p_nand_info = spi_nand_get_info(id_byte);
|
||||
p_nand_info = sfc_nand_get_info(id_byte);
|
||||
if (!p_nand_info)
|
||||
return FTL_UNSUPPORTED_FLASH;
|
||||
|
||||
|
|
@ -732,7 +747,7 @@ u32 sfc_nand_init(void)
|
|||
sfc_nand_dev.page_read_cmd = p_nand_info->read_cache_cmd_1;
|
||||
sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_1;
|
||||
if (p_nand_info->feature & FEA_4BIT_READ) {
|
||||
if (spi_nand_enable_QE() == SFC_OK) {
|
||||
if (sfc_nand_enable_QE() == SFC_OK) {
|
||||
sfc_nand_dev.read_lines = DATA_LINES_X4;
|
||||
sfc_nand_dev.page_read_cmd =
|
||||
p_nand_info->read_cache_cmd_4;
|
||||
|
|
|
|||
|
|
@ -84,6 +84,13 @@ struct SFNAND_DEV {
|
|||
u8 page_prog_cmd;
|
||||
};
|
||||
|
||||
struct nand_mega_area {
|
||||
u8 off0;
|
||||
u8 off1;
|
||||
u8 off2;
|
||||
u8 off3;
|
||||
};
|
||||
|
||||
struct nand_info {
|
||||
u32 id;
|
||||
|
||||
|
|
@ -107,8 +114,7 @@ struct nand_info {
|
|||
u8 QE_address;
|
||||
u8 QE_bits;
|
||||
|
||||
u8 spare_offs_1;
|
||||
u8 spare_offs_2;
|
||||
struct nand_mega_area meta;
|
||||
u32 (*ecc_status)(void);
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue