drm/rockchip: vop: Add support for rv1126
Change-Id: I762158891605c1a87fd7d3a7c685052ab9125b31 Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This commit is contained in:
Andy Yan
Jianhong Chen
parent
081dec1b2b
commit
a144d23d24
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@ -27,6 +27,11 @@ static const struct rockchip_crtc rv1108_vop_data = {
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.data = &rv1108_vop,
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};
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static const struct rockchip_crtc rv1126_vop_data = {
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.funcs = &rockchip_vop_funcs,
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.data = &rv1126_vop,
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};
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static const struct rockchip_crtc px30_vop_lit_data = {
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.funcs = &rockchip_vop_funcs,
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.data = &px30_vop_lit,
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@ -94,6 +99,9 @@ static const struct udevice_id rockchip_vop_ids[] = {
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}, {
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.compatible = "rockchip,rv1108-vop",
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.data = (ulong)&rv1108_vop_data,
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}, {
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.compatible = "rockchip,rv1126-vop",
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.data = (ulong)&rv1126_vop_data,
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}, {
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.compatible = "rockchip,rk3126-vop",
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.data = (ulong)&rk3036_vop_data,
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@ -44,4 +44,5 @@ extern const struct vop_data rk3399_vop_lit;
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extern const struct vop_data rk322x_vop;
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extern const struct vop_data rk3328_vop;
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extern const struct vop_data rv1108_vop;
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extern const struct vop_data rv1126_vop;
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#endif
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@ -401,6 +401,7 @@ struct vop_scl_regs {
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struct vop_win {
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const struct vop_scl_regs *scl;
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struct vop_reg gate;
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struct vop_reg enable;
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struct vop_reg format;
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struct vop_reg ymirror;
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@ -710,3 +710,92 @@ const struct vop_data rv1108_vop = {
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.line_flag = &rk3366_vop_lite_line_flag,
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.reg_len = RK3366_LIT_FRC_LOWER01_0 * 4,
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};
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static const struct vop_win rv1126_win2_data = {
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.gate = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 0),
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.enable = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 4),
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.format = VOP_REG(RV1126_WIN2_CTRL0, 0x3, 5),
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.rb_swap = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 20),
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.dsp_info = VOP_REG(RV1126_WIN2_DSP_INFO0, 0x0fff0fff, 0),
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.dsp_st = VOP_REG(RV1126_WIN2_DSP_ST0, 0x1fff1fff, 0),
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.yrgb_mst = VOP_REG(RV1126_WIN2_MST0, 0xffffffff, 0),
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.yrgb_vir = VOP_REG(RV1126_WIN2_VIR0_1, 0x1fff, 0),
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};
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static const struct vop_ctrl rv1126_ctrl_data = {
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.standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
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.axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
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.axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
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.htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
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.hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
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.vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
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.vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
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.vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
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.vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
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.dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
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.global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
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.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
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.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22),
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.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
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.core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
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.dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
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.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
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.rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
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.hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
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.hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
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.lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
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.lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
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.mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
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.mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
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.mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
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.lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
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.hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
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.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
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.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
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.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
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.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
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.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
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.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
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.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
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.dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
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.dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
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.out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
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.dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
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.cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
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.bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
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.bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
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.bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
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.bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
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.bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
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.bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
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.bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
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.bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
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.bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
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.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
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.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
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.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
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.mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
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.mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
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.mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
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.mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
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.mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
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.mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
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.mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
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.mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
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.mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
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.mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
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.mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
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.mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT,
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0xffffffff, 0),
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};
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const struct vop_data rv1126_vop = {
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.version = VOP_VERSION(2, 7),
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.max_output = {1920, 1080},
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.ctrl = &rv1126_ctrl_data,
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.win = &rv1126_win2_data,
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.line_flag = &rk3366_vop_lite_line_flag,
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.reg_len = RK3366_LIT_FLAG_REG * 4,
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};
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@ -965,4 +965,11 @@
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#define RK1808_GRF_PD_VO_CON1 0x00000444
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/* rk1808 register definition end*/
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/* RV1126 register definition start */
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#define RV1126_WIN2_CTRL0 0x0190
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#define RV1126_WIN2_VIR0_1 0x0198
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#define RV1126_WIN2_MST0 0x01a0
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#define RV1126_WIN2_DSP_INFO0 0x01a4
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#define RV1126_WIN2_DSP_ST0 0x01a8
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/* RV1126 register definition end */
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#endif /* _ROCKCHIP_VOP_REG_H */
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