* Patch by Jon Loeliger, 02 Sep 2004:
Reset monitor size back to 256 so environment can be written to flash on MPC85xx ADS and CDS releases. * Patch by Paolo Broggini, 02 Sep 2004: Make BSS clearing on ARM systems more robust * Patch by Yue Hu and Joe, 01 Sep 2004: - add PCI support for ixp425; - add EEPRO100 suppor tfor ixdp425 board. * Fix problem with protected sector detection in driver/cfi_flash.c
This commit is contained in:
wdenk
parent
15c7a8efd2
commit
a1191902ca
17
CHANGELOG
17
CHANGELOG
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@ -1,3 +1,20 @@
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======================================================================
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Changes for U-Boot 1.1.3:
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======================================================================
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* Patch by Jon Loeliger, 02 Sep 2004:
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Reset monitor size back to 256 so environment can be written
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to flash on MPC85xx ADS and CDS releases.
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* Patch by Paolo Broggini, 02 Sep 2004:
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Make BSS clearing on ARM systems more robust
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* Patch by Yue Hu and Joe, 01 Sep 2004:
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- add PCI support for ixp425;
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- add EEPRO100 suppor tfor ixdp425 board.
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* Fix problem with protected sector detection in driver/cfi_flash.c
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======================================================================
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======================================================================
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Changes for U-Boot 1.1.2:
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Changes for U-Boot 1.1.2:
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======================================================================
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======================================================================
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@ -40,7 +40,7 @@
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int
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int
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/**********************************************************/
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/**********************************************************/
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board_late_init (void)
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board_post_init (void)
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/**********************************************************/
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/**********************************************************/
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{
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{
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return (0);
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return (0);
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@ -74,3 +74,9 @@ dram_init (void)
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return (0);
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return (0);
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}
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}
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extern struct pci_controller hose;
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void pci_init_board(void)
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{
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pci_ixp_init(&hose);
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return ;
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}
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@ -168,7 +168,7 @@ clear_bss:
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clbss_l:str r2, [r0] /* clear loop... */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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add r0, r0, #4
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cmp r0, r1
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cmp r0, r1
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bne clbss_l
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ble clbss_l
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ldr pc, _start_armboot
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ldr pc, _start_armboot
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@ -195,7 +195,7 @@ clear_bss:
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clbss_l:str r2, [r0] /* clear loop... */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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add r0, r0, #4
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cmp r0, r1
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cmp r0, r1
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bne clbss_l
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ble clbss_l
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#if 0
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#if 0
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/* try doing this stuff after the relocation */
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/* try doing this stuff after the relocation */
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@ -203,7 +203,7 @@ clear_bss:
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clbss_l:str r2, [r0] /* clear loop... */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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add r0, r0, #4
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cmp r0, r1
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cmp r0, r1
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bne clbss_l
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ble clbss_l
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ldr pc, _start_armboot
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ldr pc, _start_armboot
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@ -178,7 +178,7 @@ clear_bss:
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clbss_l:str r2, [r0] /* clear loop... */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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add r0, r0, #4
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cmp r0, r1
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cmp r0, r1
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bne clbss_l
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ble clbss_l
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ldr pc, _start_armboot
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ldr pc, _start_armboot
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@ -216,7 +216,7 @@ clear_bss:
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clbss_l:str r2, [r0] /* clear loop... */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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add r0, r0, #4
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cmp r0, r1
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cmp r0, r1
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bne clbss_l
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ble clbss_l
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ldr pc,_start_armboot
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ldr pc,_start_armboot
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@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(CPU).a
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LIB = lib$(CPU).a
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START = start.o
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START = start.o
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OBJS = serial.o interrupts.o cpu.o timer.o
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OBJS = serial.o interrupts.o cpu.o timer.o pci.o
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all: .depend $(START) $(LIB)
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all: .depend $(START) $(LIB)
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@ -148,7 +148,9 @@ int dcache_status (void)
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}
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}
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/* FIXME */
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/* FIXME */
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/*
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void pci_init(void)
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void pci_init(void)
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{
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{
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return;
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return;
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}
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}
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*/
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@ -0,0 +1,613 @@
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/*
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* IXP PCI Init
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* (C) Copyright 2004 eslab.whut.edu.cn
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* Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CONFIG_PCI
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <asm/arch/ixp425.h>
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#include <asm/arch/ixp425pci.h>
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static void non_prefetch_read (unsigned int addr, unsigned int cmd,
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unsigned int *data);
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static void non_prefetch_write (unsigned int addr, unsigned int cmd,
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unsigned int data);
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static void configure_pins (void);
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static void sys_pci_gpio_clock_config (void);
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static void pci_bus_scan (void);
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static int pci_device_exists (unsigned int deviceNo);
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static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus,
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unsigned int dev, unsigned int func);
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static void sys_pci_device_bars_write (void);
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static void calc_bars (PciBar * Bars[], unsigned int nBars,
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unsigned int startAddr);
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#define PCI_MEMORY_BUS 0x00000000
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#define PCI_MEMORY_PHY 0x48000000
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#define PCI_MEMORY_SIZE 0x04000000
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#define PCI_MEM_BUS 0x40000000
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#define PCI_MEM_PHY 0x00000000
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#define PCI_MEM_SIZE 0x04000000
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#define PCI_IO_BUS 0x40000000
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#define PCI_IO_PHY 0x50000000
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#define PCI_IO_SIZE 0x10000000
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struct pci_controller hose;
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unsigned int nDevices;
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unsigned int nMBars;
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unsigned int nIOBars;
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PciBar *memBars[IXP425_PCI_MAX_BAR];
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PciBar *ioBars[IXP425_PCI_MAX_BAR];
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PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS];
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extern void out_8 (volatile unsigned *addr, char val)
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{
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*addr = val;
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}
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extern void out_le16 (volatile unsigned *addr, unsigned short val)
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{
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*addr = cpu_to_le16 (val);
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}
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extern void out_le32 (volatile unsigned *addr, unsigned int val)
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{
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*addr = cpu_to_le32 (val);
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}
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extern unsigned char in_8 (volatile unsigned *addr)
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{
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unsigned char val;
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val = *addr;
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return val;
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}
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extern unsigned short in_le16 (volatile unsigned *addr)
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{
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unsigned short val;
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val = *addr;
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val = le16_to_cpu (val);
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return val;
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}
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extern unsigned in_le32 (volatile unsigned *addr)
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{
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unsigned int val;
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val = *addr;
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val = le32_to_cpu (val);
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return val;
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}
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int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val)
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{
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unsigned int retval;
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unsigned int addr;
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||||||
|
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||||||
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/*address bits 31:28 specify the device 10:8 specify the function */
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|
/*Set the address to be read */
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addr = BIT ((31 - dev)) | (where & ~3);
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non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval);
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|
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||||||
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*val = retval;
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|
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return (OK);
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||||||
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}
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||||||
|
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||||||
|
int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val)
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|
{
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|
unsigned int n;
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|
unsigned int retval;
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|
unsigned int addr;
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||||||
|
unsigned int byteEnables;
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|
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|
n = where % 4;
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|
/*byte enables are 4 bits active low, the position of each
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|
bit maps to the byte that it enables */
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|
byteEnables =
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|
(~(BIT (n) | BIT ((n + 1)))) &
|
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|
IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
|
||||||
|
byteEnables = byteEnables << PCI_NP_CBE_BESL;
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||||||
|
/*address bits 31:28 specify the device 10:8 specify the function */
|
||||||
|
/*Set the address to be read */
|
||||||
|
addr = BIT ((31 - dev)) | (where & ~3);
|
||||||
|
non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
|
||||||
|
|
||||||
|
/*Pick out the word we are interested in */
|
||||||
|
*val = (retval >> (8 * n));
|
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|
|
||||||
|
return (OK);
|
||||||
|
}
|
||||||
|
|
||||||
|
int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val)
|
||||||
|
{
|
||||||
|
unsigned int retval;
|
||||||
|
unsigned int n;
|
||||||
|
unsigned int byteEnables;
|
||||||
|
unsigned int addr;
|
||||||
|
|
||||||
|
n = where % 4;
|
||||||
|
/*byte enables are 4 bits, active low, the position of each
|
||||||
|
bit maps to the byte that it enables */
|
||||||
|
byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
|
||||||
|
byteEnables = byteEnables << PCI_NP_CBE_BESL;
|
||||||
|
|
||||||
|
/*address bits 31:28 specify the device, 10:8 specify the function */
|
||||||
|
/*Set the address to be read */
|
||||||
|
addr = BIT ((31 - dev)) | (where & ~3);
|
||||||
|
non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
|
||||||
|
/*Pick out the byte we are interested in */
|
||||||
|
*val = (retval >> (8 * n));
|
||||||
|
|
||||||
|
return (OK);
|
||||||
|
}
|
||||||
|
|
||||||
|
int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val)
|
||||||
|
{
|
||||||
|
unsigned int addr;
|
||||||
|
unsigned int byteEnables;
|
||||||
|
unsigned int n;
|
||||||
|
unsigned int ldata;
|
||||||
|
|
||||||
|
n = where % 4;
|
||||||
|
/*byte enables are 4 bits active low, the position of each
|
||||||
|
bit maps to the byte that it enables */
|
||||||
|
byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
|
||||||
|
byteEnables = byteEnables << PCI_NP_CBE_BESL;
|
||||||
|
ldata = val << (8 * n);
|
||||||
|
/*address bits 31:28 specify the device 10:8 specify the function */
|
||||||
|
/*Set the address to be written */
|
||||||
|
addr = BIT ((31 - dev)) | (where & ~3);
|
||||||
|
non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
|
||||||
|
|
||||||
|
return (OK);
|
||||||
|
}
|
||||||
|
|
||||||
|
int pci_write_config_word (pci_dev_t dev, int where, unsigned short val)
|
||||||
|
{
|
||||||
|
unsigned int addr;
|
||||||
|
unsigned int byteEnables;
|
||||||
|
unsigned int n;
|
||||||
|
unsigned int ldata;
|
||||||
|
|
||||||
|
n = where % 4;
|
||||||
|
/*byte enables are 4 bits active low, the position of each
|
||||||
|
bit maps to the byte that it enables */
|
||||||
|
byteEnables =
|
||||||
|
(~(BIT (n) | BIT ((n + 1)))) &
|
||||||
|
IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
|
||||||
|
byteEnables = byteEnables << PCI_NP_CBE_BESL;
|
||||||
|
ldata = val << (8 * n);
|
||||||
|
/*address bits 31:28 specify the device 10:8 specify the function */
|
||||||
|
/*Set the address to be written */
|
||||||
|
addr = BIT (31 - dev) | (where & ~3);
|
||||||
|
non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
|
||||||
|
|
||||||
|
return (OK);
|
||||||
|
}
|
||||||
|
|
||||||
|
int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val)
|
||||||
|
{
|
||||||
|
unsigned int addr;
|
||||||
|
|
||||||
|
/*address bits 31:28 specify the device 10:8 specify the function */
|
||||||
|
/*Set the address to be written */
|
||||||
|
addr = BIT (31 - dev) | (where & ~3);
|
||||||
|
non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val);
|
||||||
|
|
||||||
|
return (OK);
|
||||||
|
}
|
||||||
|
|
||||||
|
void non_prefetch_read (unsigned int addr,
|
||||||
|
unsigned int cmd, unsigned int *data)
|
||||||
|
{
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
|
||||||
|
|
||||||
|
/*set up and execute the read */
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
|
||||||
|
|
||||||
|
/*The result of the read is now in np_rdata */
|
||||||
|
REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data);
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
void non_prefetch_write (unsigned int addr,
|
||||||
|
unsigned int cmd, unsigned int data)
|
||||||
|
{
|
||||||
|
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
|
||||||
|
/*set up the write */
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
|
||||||
|
/*Execute the write by writing to NP_WDATA */
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data);
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PCI controller config registers are accessed through these functions
|
||||||
|
* i.e. these allow us to set up our own BARs etc.
|
||||||
|
*/
|
||||||
|
void crp_read (unsigned int offset, unsigned int *data)
|
||||||
|
{
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset);
|
||||||
|
REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data);
|
||||||
|
}
|
||||||
|
|
||||||
|
void crp_write (unsigned int offset, unsigned int data)
|
||||||
|
{
|
||||||
|
/*The CRP address register bit 16 indicates that we want to do a write */
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET,
|
||||||
|
PCI_CRP_WRITE | offset);
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*struct pci_controller *hose*/
|
||||||
|
void pci_ixp_init (struct pci_controller *hose)
|
||||||
|
{
|
||||||
|
unsigned int regval;
|
||||||
|
|
||||||
|
hose->first_busno = 0;
|
||||||
|
hose->last_busno = 0x00;
|
||||||
|
|
||||||
|
/* System memory space */
|
||||||
|
pci_set_region (hose->regions + 0,
|
||||||
|
PCI_MEMORY_BUS,
|
||||||
|
PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY);
|
||||||
|
|
||||||
|
/* PCI memory space */
|
||||||
|
pci_set_region (hose->regions + 1,
|
||||||
|
PCI_MEM_BUS,
|
||||||
|
PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
|
||||||
|
/* PCI I/O space */
|
||||||
|
pci_set_region (hose->regions + 2,
|
||||||
|
PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
|
||||||
|
|
||||||
|
hose->region_count = 3;
|
||||||
|
|
||||||
|
pci_register_hose (hose);
|
||||||
|
|
||||||
|
/*
|
||||||
|
==========================================================
|
||||||
|
Init IXP PCI
|
||||||
|
==========================================================
|
||||||
|
*/
|
||||||
|
REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
|
||||||
|
regval |= 1 << 2;
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
|
||||||
|
|
||||||
|
configure_pins ();
|
||||||
|
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
|
||||||
|
WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13)));
|
||||||
|
udelay (533);
|
||||||
|
sys_pci_gpio_clock_config ();
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0);
|
||||||
|
udelay (100);
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
|
||||||
|
WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13));
|
||||||
|
udelay (533);
|
||||||
|
crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT);
|
||||||
|
crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT);
|
||||||
|
crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT);
|
||||||
|
crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT);
|
||||||
|
crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT);
|
||||||
|
crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT);
|
||||||
|
/*Setup PCI-AHB and AHB-PCI address mappings */
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET,
|
||||||
|
IXP425_PCI_AHBMEMBASE_DEFAULT);
|
||||||
|
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET,
|
||||||
|
IXP425_PCI_AHBIOBASE_DEFAULT);
|
||||||
|
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET,
|
||||||
|
IXP425_PCI_PCIMEMBASE_DEFAULT);
|
||||||
|
|
||||||
|
crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
|
||||||
|
|
||||||
|
REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
|
||||||
|
regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS;
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
|
||||||
|
crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
|
||||||
|
udelay (1000);
|
||||||
|
|
||||||
|
pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD);
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
|
||||||
|
| PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
|
||||||
|
#ifdef CONFIG_PCI_SCAN_SHOW
|
||||||
|
printf ("Device bus dev func deviceID vendorID \n");
|
||||||
|
#endif
|
||||||
|
pci_bus_scan ();
|
||||||
|
}
|
||||||
|
|
||||||
|
void configure_pins (void)
|
||||||
|
{
|
||||||
|
unsigned int regval;
|
||||||
|
|
||||||
|
/* Disable clock on GPIO PIN 14 */
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||||
|
WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8)));
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||||
|
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
|
||||||
|
WRITE_GPIO_REG (IXP425_GPIO_GPOER,
|
||||||
|
(((~(3 << 13)) & regval) | (0xf << 8)));
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
|
||||||
|
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
|
||||||
|
WRITE_GPIO_REG (IXP425_GPIO_GPIT2R,
|
||||||
|
(regval &
|
||||||
|
((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1)));
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
|
||||||
|
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
|
||||||
|
WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8)));
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
|
||||||
|
}
|
||||||
|
|
||||||
|
void sys_pci_gpio_clock_config (void)
|
||||||
|
{
|
||||||
|
unsigned int regval;
|
||||||
|
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||||
|
regval |= 0x1 << 4;
|
||||||
|
WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||||
|
READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||||
|
regval |= 0x1 << 8;
|
||||||
|
WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||||
|
}
|
||||||
|
|
||||||
|
void pci_bus_scan (void)
|
||||||
|
{
|
||||||
|
unsigned int bus = 0, dev, func = 0;
|
||||||
|
unsigned short data16;
|
||||||
|
unsigned int data32;
|
||||||
|
unsigned char intPin;
|
||||||
|
|
||||||
|
/* Assign first device to ourselves */
|
||||||
|
devices[0].bus = 0;
|
||||||
|
devices[0].device = 0;
|
||||||
|
devices[0].func = 0;
|
||||||
|
|
||||||
|
crp_read (PCI_CFG_VENDOR_ID, &data32);
|
||||||
|
|
||||||
|
devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK;
|
||||||
|
devices[0].device_id = data32 >> 16;
|
||||||
|
devices[0].error = FALSE;
|
||||||
|
devices[0].bar[NO_BAR].size = 0; /*dummy - required */
|
||||||
|
|
||||||
|
nDevices = 1;
|
||||||
|
|
||||||
|
nMBars = 0;
|
||||||
|
nIOBars = 0;
|
||||||
|
|
||||||
|
for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) {
|
||||||
|
|
||||||
|
/*Check whether a device is present */
|
||||||
|
if (pci_device_exists (dev) != TRUE) {
|
||||||
|
|
||||||
|
/*Clear error bits in ISR, write 1 to clear */
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
|
||||||
|
| PCI_ISR_PFE | PCI_ISR_PPE |
|
||||||
|
PCI_ISR_AHBE);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*A device is present, add an entry to the array */
|
||||||
|
devices[nDevices].bus = bus;
|
||||||
|
devices[nDevices].device = dev;
|
||||||
|
devices[nDevices].func = func;
|
||||||
|
|
||||||
|
pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16);
|
||||||
|
|
||||||
|
devices[nDevices].vendor_id = data16;
|
||||||
|
|
||||||
|
pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16);
|
||||||
|
devices[nDevices].device_id = data16;
|
||||||
|
|
||||||
|
/*The device is functioning correctly, set error to FALSE */
|
||||||
|
devices[nDevices].error = FALSE;
|
||||||
|
|
||||||
|
/*Figure out what BARs are on this device */
|
||||||
|
sys_pci_bar_info_get (nDevices, bus, dev, func);
|
||||||
|
/*Figure out what INTX# line the card uses */
|
||||||
|
pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin);
|
||||||
|
|
||||||
|
/*assign the appropriate irq line */
|
||||||
|
if (intPin > PCI_IRQ_LINES) {
|
||||||
|
devices[nDevices].error = TRUE;
|
||||||
|
} else if (intPin != 0) {
|
||||||
|
/*This device uses an interrupt line */
|
||||||
|
/*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */
|
||||||
|
devices[nDevices].irq = intPin;
|
||||||
|
}
|
||||||
|
#ifdef CONFIG_PCI_SCAN_SHOW
|
||||||
|
printf ("%06d %03d %03d %04d %08d %08x\n", nDevices,
|
||||||
|
devices[nDevices].vendor_id);
|
||||||
|
#endif
|
||||||
|
nDevices++;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE);
|
||||||
|
sys_pci_device_bars_write ();
|
||||||
|
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
|
||||||
|
| PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
|
||||||
|
}
|
||||||
|
|
||||||
|
void sys_pci_bar_info_get (unsigned int devnum,
|
||||||
|
unsigned int bus,
|
||||||
|
unsigned int dev, unsigned int func)
|
||||||
|
{
|
||||||
|
unsigned int data32;
|
||||||
|
unsigned int tmp;
|
||||||
|
unsigned int size;
|
||||||
|
|
||||||
|
pci_write_config_dword (devnum,
|
||||||
|
PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY);
|
||||||
|
pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32);
|
||||||
|
|
||||||
|
devices[devnum].bar[0].address = (data32 & 1);
|
||||||
|
|
||||||
|
if (data32 & 1) {
|
||||||
|
/* IO space */
|
||||||
|
tmp = data32 & ~0x3;
|
||||||
|
size = ~(tmp - 1);
|
||||||
|
devices[devnum].bar[0].size = size;
|
||||||
|
|
||||||
|
if (nIOBars < IXP425_PCI_MAX_BAR) {
|
||||||
|
ioBars[nIOBars++] = &devices[devnum].bar[0];
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
/* Mem space */
|
||||||
|
tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
|
||||||
|
size = ~(tmp - 1);
|
||||||
|
devices[devnum].bar[0].size = size;
|
||||||
|
|
||||||
|
if (nMBars < IXP425_PCI_MAX_BAR) {
|
||||||
|
memBars[nMBars++] = &devices[devnum].bar[0];
|
||||||
|
} else {
|
||||||
|
devices[devnum].error = TRUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
devices[devnum].bar[1].size = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void sortBars (PciBar * Bars[], unsigned int nBars)
|
||||||
|
{
|
||||||
|
unsigned int i, j;
|
||||||
|
PciBar *tmp;
|
||||||
|
|
||||||
|
if (nBars == 0) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Sort biggest to smallest */
|
||||||
|
for (i = 0; i < nBars - 1; i++) {
|
||||||
|
for (j = i + 1; j < nBars; j++) {
|
||||||
|
if (Bars[j]->size > Bars[i]->size) {
|
||||||
|
/* swap them */
|
||||||
|
tmp = Bars[i];
|
||||||
|
Bars[i] = Bars[j];
|
||||||
|
Bars[j] = tmp;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr)
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
if (nBars == 0) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < nBars; i++) {
|
||||||
|
Bars[i]->address |= startAddr;
|
||||||
|
startAddr += Bars[i]->size;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void sys_pci_device_bars_write (void)
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
int addr;
|
||||||
|
|
||||||
|
for (i = 1; i < nDevices; i++) {
|
||||||
|
if (devices[i].error) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
pci_write_config_dword (devices[i].device,
|
||||||
|
PCI_CFG_BASE_ADDRESS_0,
|
||||||
|
devices[i].bar[0].address);
|
||||||
|
addr = BIT (31 -
|
||||||
|
devices[i].
|
||||||
|
device) | (0 << PCI_NP_AD_FUNCSL) |
|
||||||
|
(PCI_CFG_BASE_ADDRESS_0) & ~3;
|
||||||
|
pci_write_config_dword (devices[i].device,
|
||||||
|
PCI_CFG_DEV_INT_LINE, devices[i].irq);
|
||||||
|
|
||||||
|
pci_write_config_word (devices[i].device,
|
||||||
|
PCI_CFG_COMMAND, INITIAL_PCI_CMD);
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int pci_device_exists (unsigned int deviceNo)
|
||||||
|
{
|
||||||
|
unsigned int vendorId;
|
||||||
|
unsigned int regval;
|
||||||
|
|
||||||
|
pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId);
|
||||||
|
|
||||||
|
/* There are two ways to find out an empty device.
|
||||||
|
* 1. check Master Abort bit after the access.
|
||||||
|
* 2. check whether the vendor id read back is 0x0.
|
||||||
|
*/
|
||||||
|
REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval);
|
||||||
|
if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) {
|
||||||
|
return TRUE;
|
||||||
|
}
|
||||||
|
/*no device present, make sure that the master abort bit is reset */
|
||||||
|
|
||||||
|
REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE);
|
||||||
|
return FALSE;
|
||||||
|
}
|
||||||
|
|
||||||
|
pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo)
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
unsigned int devdidvid;
|
||||||
|
unsigned int didvid;
|
||||||
|
unsigned int vendorId, deviceId;
|
||||||
|
|
||||||
|
vendorId = ids->vendor;
|
||||||
|
deviceId = ids->device;
|
||||||
|
didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) |
|
||||||
|
(vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK);
|
||||||
|
|
||||||
|
for (i = devNo + 1; i < nDevices; i++) {
|
||||||
|
|
||||||
|
pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID,
|
||||||
|
&devdidvid);
|
||||||
|
|
||||||
|
if (devdidvid == didvid) {
|
||||||
|
return devices[i].device;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_PCI */
|
||||||
|
|
@ -159,11 +159,12 @@ reset:
|
||||||
str r1, [r2]
|
str r1, [r2]
|
||||||
|
|
||||||
/* make sure flash is visible at 0 */
|
/* make sure flash is visible at 0 */
|
||||||
|
#if 0
|
||||||
ldr r2, =IXP425_EXP_CFG0
|
ldr r2, =IXP425_EXP_CFG0
|
||||||
ldr r1, [r2]
|
ldr r1, [r2]
|
||||||
orr r1, r1, #0x80000000
|
orr r1, r1, #0x80000000
|
||||||
str r1, [r2]
|
str r1, [r2]
|
||||||
|
#endif
|
||||||
mov r1, #CFG_SDR_CONFIG
|
mov r1, #CFG_SDR_CONFIG
|
||||||
ldr r2, =IXP425_SDR_CONFIG
|
ldr r2, =IXP425_SDR_CONFIG
|
||||||
str r1, [r2]
|
str r1, [r2]
|
||||||
|
|
@ -198,7 +199,7 @@ reset:
|
||||||
bne 111b
|
bne 111b
|
||||||
|
|
||||||
/* set mode register in sdram */
|
/* set mode register in sdram */
|
||||||
mov r1, #1
|
mov r1, #CFG_SDR_MODE_CONFIG
|
||||||
str r1, [r4]
|
str r1, [r4]
|
||||||
DELAY_FOR 0x4000, r0
|
DELAY_FOR 0x4000, r0
|
||||||
|
|
||||||
|
|
@ -295,7 +296,7 @@ clear_bss:
|
||||||
clbss_l:str r2, [r0] /* clear loop... */
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
add r0, r0, #4
|
add r0, r0, #4
|
||||||
cmp r0, r1
|
cmp r0, r1
|
||||||
bne clbss_l
|
ble clbss_l
|
||||||
|
|
||||||
ldr pc, _start_armboot
|
ldr pc, _start_armboot
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -187,7 +187,7 @@ clear_bss:
|
||||||
clbss_l:str r2, [r0] /* clear loop... */
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
add r0, r0, #4
|
add r0, r0, #4
|
||||||
cmp r0, r1
|
cmp r0, r1
|
||||||
bne clbss_l
|
ble clbss_l
|
||||||
|
|
||||||
ldr pc, _start_armboot
|
ldr pc, _start_armboot
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -147,7 +147,7 @@ clear_bss:
|
||||||
clbss_l:str r2, [r0] /* clear loop... */
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
add r0, r0, #4
|
add r0, r0, #4
|
||||||
cmp r0, r1
|
cmp r0, r1
|
||||||
bne clbss_l
|
ble clbss_l
|
||||||
|
|
||||||
ldr pc, _start_armboot
|
ldr pc, _start_armboot
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -160,7 +160,7 @@ clear_bss:
|
||||||
clbss_l:str r2, [r0] /* clear loop... */
|
clbss_l:str r2, [r0] /* clear loop... */
|
||||||
add r0, r0, #4
|
add r0, r0, #4
|
||||||
cmp r0, r1
|
cmp r0, r1
|
||||||
bne clbss_l
|
ble clbss_l
|
||||||
|
|
||||||
ldr pc, _start_armboot
|
ldr pc, _start_armboot
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1066,10 +1066,22 @@ static ulong flash_get_size (ulong base, int banknum)
|
||||||
for (j = 0; j < erase_region_count; j++) {
|
for (j = 0; j < erase_region_count; j++) {
|
||||||
info->start[sect_cnt] = sector;
|
info->start[sect_cnt] = sector;
|
||||||
sector += (erase_region_size * size_ratio);
|
sector += (erase_region_size * size_ratio);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Only read protection status from supported devices (intel...)
|
||||||
|
*/
|
||||||
|
switch (info->vendor) {
|
||||||
|
case CFI_CMDSET_INTEL_EXTENDED:
|
||||||
|
case CFI_CMDSET_INTEL_STANDARD:
|
||||||
info->protect[sect_cnt] =
|
info->protect[sect_cnt] =
|
||||||
flash_isset (info, sect_cnt,
|
flash_isset (info, sect_cnt,
|
||||||
FLASH_OFFSET_PROTECT,
|
FLASH_OFFSET_PROTECT,
|
||||||
FLASH_STATUS_PROTECT);
|
FLASH_STATUS_PROTECT);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
info->protect[sect_cnt] = 0; /* default: not protected */
|
||||||
|
}
|
||||||
|
|
||||||
sect_cnt++;
|
sect_cnt++;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -37,16 +37,6 @@
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
|
|
||||||
#ifdef DEBUG
|
|
||||||
#define DEBUGF(x...) printf(x)
|
|
||||||
#else
|
|
||||||
#define DEBUGF(x...)
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
/*
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define PCI_HOSE_OP(rw, size, type) \
|
#define PCI_HOSE_OP(rw, size, type) \
|
||||||
int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
|
int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
|
||||||
pci_dev_t dev, \
|
pci_dev_t dev, \
|
||||||
|
|
@ -62,6 +52,7 @@ PCI_HOSE_OP(write, byte, u8)
|
||||||
PCI_HOSE_OP(write, word, u16)
|
PCI_HOSE_OP(write, word, u16)
|
||||||
PCI_HOSE_OP(write, dword, u32)
|
PCI_HOSE_OP(write, dword, u32)
|
||||||
|
|
||||||
|
#ifndef CONFIG_IXP425
|
||||||
#define PCI_OP(rw, size, type, error_code) \
|
#define PCI_OP(rw, size, type, error_code) \
|
||||||
int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
|
int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
|
||||||
{ \
|
{ \
|
||||||
|
|
@ -82,6 +73,7 @@ PCI_OP(read, dword, u32 *, *value = 0xffffffff)
|
||||||
PCI_OP(write, byte, u8, )
|
PCI_OP(write, byte, u8, )
|
||||||
PCI_OP(write, word, u16, )
|
PCI_OP(write, word, u16, )
|
||||||
PCI_OP(write, dword, u32, )
|
PCI_OP(write, dword, u32, )
|
||||||
|
#endif /* CONFIG_IXP425 */
|
||||||
|
|
||||||
#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
|
#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
|
||||||
int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
|
int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
|
||||||
|
|
@ -150,9 +142,11 @@ struct pci_controller *pci_bus_to_hose (int bus)
|
||||||
if (bus >= hose->first_busno && bus <= hose->last_busno)
|
if (bus >= hose->first_busno && bus <= hose->last_busno)
|
||||||
return hose;
|
return hose;
|
||||||
|
|
||||||
|
debug ("pci_bus_to_hose() failed\n");
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifndef CONFIG_IXP425
|
||||||
pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
|
pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
|
||||||
{
|
{
|
||||||
struct pci_controller * hose;
|
struct pci_controller * hose;
|
||||||
|
|
@ -208,6 +202,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
|
||||||
|
|
||||||
return (-1);
|
return (-1);
|
||||||
}
|
}
|
||||||
|
#endif /* CONFIG_IXP425 */
|
||||||
|
|
||||||
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
|
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
|
||||||
{
|
{
|
||||||
|
|
@ -300,7 +295,7 @@ int pci_hose_config_device(struct pci_controller *hose,
|
||||||
unsigned char pin;
|
unsigned char pin;
|
||||||
int bar, found_mem64;
|
int bar, found_mem64;
|
||||||
|
|
||||||
DEBUGF ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
|
debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
|
||||||
io, mem, command);
|
io, mem, command);
|
||||||
|
|
||||||
pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
|
pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
|
||||||
|
|
@ -454,7 +449,7 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus)
|
||||||
if (!PCI_FUNC(dev))
|
if (!PCI_FUNC(dev))
|
||||||
found_multi = header_type & 0x80;
|
found_multi = header_type & 0x80;
|
||||||
|
|
||||||
DEBUGF("PCI Scan: Found Bus %d, Device %d, Function %d\n",
|
debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
|
||||||
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
|
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
|
||||||
|
|
||||||
pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
|
pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,312 @@
|
||||||
|
/*
|
||||||
|
* IXP PCI Init
|
||||||
|
* (C) Copyright 2004 eslab.whut.edu.cn
|
||||||
|
* Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _IXP425PCI_H_
|
||||||
|
#define _IXP425PCI_H_
|
||||||
|
|
||||||
|
#define TRUE 1
|
||||||
|
#define FALSE 0
|
||||||
|
#define OK 0
|
||||||
|
#define ERROR -1
|
||||||
|
#define BOOL int
|
||||||
|
|
||||||
|
#define IXP425_PCI_MAX_BAR_PER_FUNC 6
|
||||||
|
#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
|
||||||
|
IXP425_PCI_MAX_FUNC_ON_BUS)
|
||||||
|
|
||||||
|
enum PciBarId
|
||||||
|
{
|
||||||
|
CSR_BAR=0,
|
||||||
|
IO_BAR,
|
||||||
|
SD_BAR,
|
||||||
|
NO_BAR
|
||||||
|
};
|
||||||
|
|
||||||
|
/*Base address register descriptor*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
unsigned int size;
|
||||||
|
unsigned int address;
|
||||||
|
} PciBar;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
unsigned int bus;
|
||||||
|
unsigned int device;
|
||||||
|
unsigned int func;
|
||||||
|
unsigned int irq;
|
||||||
|
BOOL error;
|
||||||
|
unsigned short vendor_id;
|
||||||
|
unsigned short device_id;
|
||||||
|
/*We need an extra entry in this array for dummy placeholder*/
|
||||||
|
PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
|
||||||
|
} PciDevice;
|
||||||
|
|
||||||
|
/* Mask definitions*/
|
||||||
|
#define IXP425_PCI_TOP_WORD_OF_LONG_MASK 0xffff0000
|
||||||
|
#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK 0xff000000
|
||||||
|
#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK 0x0000ffff
|
||||||
|
#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff
|
||||||
|
#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f
|
||||||
|
#define IXP425_PCI_MAX_UINT32 0xffffffff
|
||||||
|
|
||||||
|
|
||||||
|
#define IXP425_PCI_BAR_QUERY 0xffffffff
|
||||||
|
|
||||||
|
#define IXP425_PCI_BAR_MEM_BASE 0x100000
|
||||||
|
#define IXP425_PCI_BAR_IO_BASE 0x000000
|
||||||
|
|
||||||
|
/*define the maximum number of bus segments - we support a single segment*/
|
||||||
|
#define IXP425_PCI_MAX_BUS 1
|
||||||
|
/*define the maximum number of cards per bus segment*/
|
||||||
|
#define IXP425_PCI_MAX_DEV 4
|
||||||
|
/*define the maximum number of functions per device*/
|
||||||
|
#define IXP425_PCI_MAX_FUNC 8
|
||||||
|
/* define the maximum number of separate functions that we can
|
||||||
|
potentially have on the bus*/
|
||||||
|
#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC * \
|
||||||
|
IXP425_PCI_MAX_DEV * \
|
||||||
|
IXP425_PCI_MAX_BUS)
|
||||||
|
/*define the maximum number of BARs per function*/
|
||||||
|
#define IXP425_PCI_MAX_BAR_PER_FUNC 6
|
||||||
|
#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
|
||||||
|
IXP425_PCI_MAX_FUNC_ON_BUS)
|
||||||
|
|
||||||
|
#define PCI_NP_CBE_BESL (4)
|
||||||
|
#define PCI_NP_AD_FUNCSL (8)
|
||||||
|
|
||||||
|
#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
|
||||||
|
#define REG_READ(b,o,v) ((v)=(*(volatile unsigned int*)((b+o))))
|
||||||
|
|
||||||
|
#define PCI_DELAY 500
|
||||||
|
#define USEC_LOOP_COUNT 533
|
||||||
|
#define PCI_SETTLE_USEC 200
|
||||||
|
#define PCI_MIN_RESET_ASSERT_USEC 2000
|
||||||
|
|
||||||
|
/*Register addressing definitions for PCI controller configuration
|
||||||
|
and status registers*/
|
||||||
|
|
||||||
|
#define PCI_CSR_BASE (0xC0000000)
|
||||||
|
/*
|
||||||
|
#define PCI_NP_AD_OFFSET (0x00)
|
||||||
|
#define PCI_NP_CBE_OFFSET (0x04)
|
||||||
|
#define PCI_NP_WDATA_OFFSET (0x08)
|
||||||
|
#define PCI_NP_RDATA_OFFSET (0x0C)
|
||||||
|
#define PCI_CRP_OFFSET (0x10)
|
||||||
|
#define PCI_CRP_WDATA_OFFSET (0x14)
|
||||||
|
#define PCI_CRP_RDATA_OFFSET (0x18)
|
||||||
|
#define PCI_CSR_OFFSET (0x1C)
|
||||||
|
#define PCI_ISR_OFFSET (0x20)
|
||||||
|
#define PCI_INTEN_OFFSET (0x24)
|
||||||
|
#define PCI_DMACTRL_OFFSET (0x28)
|
||||||
|
#define PCI_AHBMEMBASE_OFFSET (0x2C)
|
||||||
|
#define PCI_AHBIOBASE_OFFSET (0x30)
|
||||||
|
#define PCI_PCIMEMBASE_OFFSET (0x34)
|
||||||
|
#define PCI_AHBDOORBELL_OFFSET (0x38)
|
||||||
|
#define PCI_PCIDOORBELL_OFFSET (0x3C)
|
||||||
|
#define PCI_ATPDMA0_AHBADDR (0x40)
|
||||||
|
#define PCI_ATPDMA0_PCIADDR (0x44)
|
||||||
|
#define PCI_ATPDMA0_LENADDR (0x48)
|
||||||
|
#define PCI_ATPDMA1_AHBADDR (0x4C)
|
||||||
|
#define PCI_ATPDMA1_PCIADDR (0x50)
|
||||||
|
#define PCI_ATPDMA1_LENADDR (0x54)
|
||||||
|
#define PCI_PTADMA0_AHBADDR (0x58)
|
||||||
|
#define PCI_PTADMA0_PCIADDR (0x5C)
|
||||||
|
#define PCI_PTADMA0_LENADDR (0x60)
|
||||||
|
#define PCI_PTADMA1_AHBADDR (0x64)
|
||||||
|
#define PCI_PTADMA1_PCIADDR (0x68)
|
||||||
|
#define PCI_PTADMA1_LENADDR (0x6C)
|
||||||
|
*/
|
||||||
|
/*Non prefetch registers bit definitions*/
|
||||||
|
/*
|
||||||
|
#define NP_CMD_INTACK (0x0)
|
||||||
|
#define NP_CMD_SPECIAL (0x1)
|
||||||
|
#define NP_CMD_IOREAD (0x2)
|
||||||
|
#define NP_CMD_IOWRITE (0x3)
|
||||||
|
#define NP_CMD_MEMREAD (0x6)
|
||||||
|
#define NP_CMD_MEMWRITE (0x7)
|
||||||
|
#define NP_CMD_CONFIGREAD (0xa)
|
||||||
|
#define NP_CMD_CONFIGWRITE (0xb)
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*define the default setting of the AHB memory base reg*/
|
||||||
|
#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
|
||||||
|
#define IXP425_PCI_AHBIOBASE_DEFAULT 0x0
|
||||||
|
#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
|
||||||
|
|
||||||
|
/*define the default settings for the controller's BARs*/
|
||||||
|
#ifdef IXP425_PCI_SIMPLE_MAPPING
|
||||||
|
#define IXP425_PCI_BAR_0_DEFAULT 0x00000000
|
||||||
|
#define IXP425_PCI_BAR_1_DEFAULT 0x01000000
|
||||||
|
#define IXP425_PCI_BAR_2_DEFAULT 0x02000000
|
||||||
|
#define IXP425_PCI_BAR_3_DEFAULT 0x03000000
|
||||||
|
#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
|
||||||
|
#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
|
||||||
|
#else
|
||||||
|
#define IXP425_PCI_BAR_0_DEFAULT 0x40000000
|
||||||
|
#define IXP425_PCI_BAR_1_DEFAULT 0x41000000
|
||||||
|
#define IXP425_PCI_BAR_2_DEFAULT 0x42000000
|
||||||
|
#define IXP425_PCI_BAR_3_DEFAULT 0x43000000
|
||||||
|
#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
|
||||||
|
#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*Configuration Port register bit definitions*/
|
||||||
|
#define PCI_CRP_WRITE BIT(16)
|
||||||
|
|
||||||
|
/*ISR (Interrupt status) Register bit definitions*/
|
||||||
|
#define PCI_ISR_PSE BIT(0)
|
||||||
|
#define PCI_ISR_PFE BIT(1)
|
||||||
|
#define PCI_ISR_PPE BIT(2)
|
||||||
|
#define PCI_ISR_AHBE BIT(3)
|
||||||
|
#define PCI_ISR_APDC BIT(4)
|
||||||
|
#define PCI_ISR_PADC BIT(5)
|
||||||
|
#define PCI_ISR_ADB BIT(6)
|
||||||
|
#define PCI_ISR_PDB BIT(7)
|
||||||
|
|
||||||
|
/*INTEN (Interrupt Enable) Register bit definitions*/
|
||||||
|
#define PCI_INTEN_PSE BIT(0)
|
||||||
|
#define PCI_INTEN_PFE BIT(1)
|
||||||
|
#define PCI_INTEN_PPE BIT(2)
|
||||||
|
#define PCI_INTEN_AHBE BIT(3)
|
||||||
|
#define PCI_INTEN_APDC BIT(4)
|
||||||
|
#define PCI_INTEN_PADC BIT(5)
|
||||||
|
#define PCI_INTEN_ADB BIT(6)
|
||||||
|
#define PCI_INTEN_PDB BIT(7)
|
||||||
|
|
||||||
|
/*PCI configuration regs.*/
|
||||||
|
|
||||||
|
#define PCI_CFG_VENDOR_ID 0x00
|
||||||
|
#define PCI_CFG_DEVICE_ID 0x02
|
||||||
|
#define PCI_CFG_COMMAND 0x04
|
||||||
|
#define PCI_CFG_STATUS 0x06
|
||||||
|
#define PCI_CFG_REVISION 0x08
|
||||||
|
#define PCI_CFG_PROGRAMMING_IF 0x09
|
||||||
|
#define PCI_CFG_SUBCLASS 0x0a
|
||||||
|
#define PCI_CFG_CLASS 0x0b
|
||||||
|
#define PCI_CFG_CACHE_LINE_SIZE 0x0c
|
||||||
|
#define PCI_CFG_LATENCY_TIMER 0x0d
|
||||||
|
#define PCI_CFG_HEADER_TYPE 0x0e
|
||||||
|
#define PCI_CFG_BIST 0x0f
|
||||||
|
#define PCI_CFG_BASE_ADDRESS_0 0x10
|
||||||
|
#define PCI_CFG_BASE_ADDRESS_1 0x14
|
||||||
|
#define PCI_CFG_BASE_ADDRESS_2 0x18
|
||||||
|
#define PCI_CFG_BASE_ADDRESS_3 0x1c
|
||||||
|
#define PCI_CFG_BASE_ADDRESS_4 0x20
|
||||||
|
#define PCI_CFG_BASE_ADDRESS_5 0x24
|
||||||
|
#define PCI_CFG_CIS 0x28
|
||||||
|
#define PCI_CFG_SUB_VENDOR_ID 0x2c
|
||||||
|
#define PCI_CFG_SUB_SYSTEM_ID 0x2e
|
||||||
|
#define PCI_CFG_EXPANSION_ROM 0x30
|
||||||
|
#define PCI_CFG_RESERVED_0 0x34
|
||||||
|
#define PCI_CFG_RESERVED_1 0x38
|
||||||
|
#define PCI_CFG_DEV_INT_LINE 0x3c
|
||||||
|
#define PCI_CFG_DEV_INT_PIN 0x3d
|
||||||
|
#define PCI_CFG_MIN_GRANT 0x3e
|
||||||
|
#define PCI_CFG_MAX_LATENCY 0x3f
|
||||||
|
#define PCI_CFG_SPECIAL_USE 0x41
|
||||||
|
#define PCI_CFG_MODE 0x43
|
||||||
|
|
||||||
|
/*Specify the initial command we send to PCI devices*/
|
||||||
|
#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE \
|
||||||
|
| PCI_CMD_MEM_ENABLE \
|
||||||
|
| PCI_CMD_MASTER_ENABLE \
|
||||||
|
| PCI_CMD_WI_ENABLE)
|
||||||
|
|
||||||
|
/*define the sub vendor and subsystem to be used */
|
||||||
|
#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
|
||||||
|
|
||||||
|
#define PCI_IRQ_LINES 4
|
||||||
|
|
||||||
|
#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
|
||||||
|
#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
|
||||||
|
#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
|
||||||
|
#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
|
||||||
|
#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
|
||||||
|
#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
|
||||||
|
#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
|
||||||
|
#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
|
||||||
|
#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
|
||||||
|
#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
|
||||||
|
|
||||||
|
|
||||||
|
/*CSR Register bit definitions*/
|
||||||
|
#define PCI_CSR_HOST BIT(0)
|
||||||
|
#define PCI_CSR_ARBEN BIT(1)
|
||||||
|
#define PCI_CSR_ADS BIT(2)
|
||||||
|
#define PCI_CSR_PDS BIT(3)
|
||||||
|
#define PCI_CSR_ABE BIT(4)
|
||||||
|
#define PCI_CSR_DBT BIT(5)
|
||||||
|
#define PCI_CSR_ASE BIT(8)
|
||||||
|
#define PCI_CSR_IC BIT(15)
|
||||||
|
|
||||||
|
/*Configuration command bit definitions*/
|
||||||
|
#define PCI_CFG_CMD_IOAE BIT(0)
|
||||||
|
#define PCI_CFG_CMD_MAE BIT(1)
|
||||||
|
#define PCI_CFG_CMD_BME BIT(2)
|
||||||
|
#define PCI_CFG_CMD_MWIE BIT(4)
|
||||||
|
#define PCI_CFG_CMD_SER BIT(8)
|
||||||
|
#define PCI_CFG_CMD_FBBE BIT(9)
|
||||||
|
#define PCI_CFG_CMD_MDPE BIT(24)
|
||||||
|
#define PCI_CFG_CMD_STA BIT(27)
|
||||||
|
#define PCI_CFG_CMD_RTA BIT(28)
|
||||||
|
#define PCI_CFG_CMD_RMA BIT(29)
|
||||||
|
#define PCI_CFG_CMD_SSE BIT(30)
|
||||||
|
#define PCI_CFG_CMD_DPE BIT(31)
|
||||||
|
|
||||||
|
/*DMACTRL DMA Control and status Register*/
|
||||||
|
#define PCI_DMACTRL_APDCEN BIT(0)
|
||||||
|
#define PCI_DMACTRL_APDC0 BIT(4)
|
||||||
|
#define PCI_DMACTRL_APDE0 BIT(5)
|
||||||
|
#define PCI_DMACTRL_APDC1 BIT(6)
|
||||||
|
#define PCI_DMACTRL_APDE1 BIT(7)
|
||||||
|
#define PCI_DMACTRL_PADCEN BIT(8)
|
||||||
|
#define PCI_DMACTRL_PADC0 BIT(12)
|
||||||
|
#define PCI_DMACTRL_PADE0 BIT(13)
|
||||||
|
#define PCI_DMACTRL_PADC1 BIT(14)
|
||||||
|
#define PCI_DMACTRL_PADE1 BIT(15)
|
||||||
|
|
||||||
|
/* GPIO related register */
|
||||||
|
#undef IXP425_GPIO_GPOUTR
|
||||||
|
#undef IXP425_GPIO_GPOER
|
||||||
|
#undef IXP425_GPIO_GPINR
|
||||||
|
#undef IXP425_GPIO_GPISR
|
||||||
|
#undef IXP425_GPIO_GPIT1R
|
||||||
|
#undef IXP425_GPIO_GPIT2R
|
||||||
|
#undef IXP425_GPIO_GPCLKR
|
||||||
|
|
||||||
|
#define IXP425_GPIO_GPOUTR 0xC8004000
|
||||||
|
#define IXP425_GPIO_GPOER 0xC8004004
|
||||||
|
#define IXP425_GPIO_GPINR 0xC8004008
|
||||||
|
#define IXP425_GPIO_GPISR 0xC800400C
|
||||||
|
#define IXP425_GPIO_GPIT1R 0xC8004010
|
||||||
|
#define IXP425_GPIO_GPIT2R 0xC8004014
|
||||||
|
#define IXP425_GPIO_GPCLKR 0xC8004018
|
||||||
|
|
||||||
|
#define READ_GPIO_REG(addr,val) \
|
||||||
|
(val) = *((volatile int *)(addr));
|
||||||
|
#define WRITE_GPIO_REG(addr,val) \
|
||||||
|
*((volatile int *)(addr)) = (val);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -264,7 +264,7 @@
|
||||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||||
|
|
||||||
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 256 kB for Mon */
|
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||||
|
|
||||||
/* Serial Port */
|
/* Serial Port */
|
||||||
|
|
|
||||||
|
|
@ -248,7 +248,7 @@ extern unsigned long get_clock_freq(void);
|
||||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||||
|
|
||||||
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
|
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||||
|
|
||||||
/* Serial Port */
|
/* Serial Port */
|
||||||
|
|
|
||||||
|
|
@ -248,7 +248,7 @@ extern unsigned long get_clock_freq(void);
|
||||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||||
|
|
||||||
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
|
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||||
|
|
||||||
/* Serial Port */
|
/* Serial Port */
|
||||||
|
|
|
||||||
|
|
@ -267,7 +267,7 @@
|
||||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||||
|
|
||||||
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 256 kB for Mon */
|
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||||
|
|
||||||
/* Serial Port */
|
/* Serial Port */
|
||||||
|
|
|
||||||
|
|
@ -56,17 +56,20 @@
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
|
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_PCI)
|
||||||
|
|
||||||
|
#define CONFIG_PCI
|
||||||
|
#define CONFIG_NET_MULTI
|
||||||
|
#define CONFIG_EEPRO100
|
||||||
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||||
/* These are u-boot generic parameters */
|
/* These are u-boot generic parameters */
|
||||||
#include <cmd_confdefs.h>
|
#include <cmd_confdefs.h>
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 3
|
#define CONFIG_BOOTDELAY 3
|
||||||
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
|
/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/
|
||||||
#define CONFIG_NETMASK 255.255.0.0
|
#define CONFIG_NETMASK 255.255.255.0
|
||||||
#define CONFIG_IPADDR 192.168.0.21
|
#define CONFIG_IPADDR 192.168.0.21
|
||||||
#define CONFIG_SERVERIP 192.168.0.250
|
#define CONFIG_SERVERIP 192.168.0.148
|
||||||
#define CONFIG_BOOTCOMMAND "bootm 50040000"
|
#define CONFIG_BOOTCOMMAND "bootm 50040000"
|
||||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
|
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
|
||||||
#define CONFIG_CMDLINE_TAG
|
#define CONFIG_CMDLINE_TAG
|
||||||
|
|
@ -148,6 +151,7 @@
|
||||||
* SDRAM settings
|
* SDRAM settings
|
||||||
*/
|
*/
|
||||||
#define CFG_SDR_CONFIG 0xd
|
#define CFG_SDR_CONFIG 0xd
|
||||||
|
#define CFG_SDR_MODE_CONFIG 0x1
|
||||||
#define CFG_SDRAM_REFRESH_CNT 0x81a
|
#define CFG_SDRAM_REFRESH_CNT 0x81a
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
||||||
|
|
@ -24,6 +24,6 @@
|
||||||
#ifndef __VERSION_H__
|
#ifndef __VERSION_H__
|
||||||
#define __VERSION_H__
|
#define __VERSION_H__
|
||||||
|
|
||||||
#define U_BOOT_VERSION "U-Boot 1.1.2"
|
#define U_BOOT_VERSION "U-Boot 1.1.3"
|
||||||
|
|
||||||
#endif /* __VERSION_H__ */
|
#endif /* __VERSION_H__ */
|
||||||
|
|
|
||||||
|
|
@ -341,7 +341,10 @@ void start_armboot (void)
|
||||||
#ifdef BOARD_LATE_INIT
|
#ifdef BOARD_LATE_INIT
|
||||||
board_late_init ();
|
board_late_init ();
|
||||||
#endif
|
#endif
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
|
||||||
|
puts ("Net: ");
|
||||||
|
eth_initialize(gd->bd);
|
||||||
|
#endif
|
||||||
/* main_loop() can return to retry autoboot, if so just run it again. */
|
/* main_loop() can return to retry autoboot, if so just run it again. */
|
||||||
for (;;) {
|
for (;;) {
|
||||||
main_loop ();
|
main_loop ();
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue